DP83256VF National Semiconductor, DP83256VF Datasheet - Page 8

• Manufacturer Part Number: DP83256VF
• Description: IC FDDI LAYER CTRLR 160PQFP
• Manufacturer: National Semiconductor
• Series: PLAYER+™r

Specifications of DP83256VF

• Controller Type: physical layer controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Interface: -
• Other names: *DP83256VF

3 0 Functional Description
Since the loop gain is held constant regardless of the in-
coming signal edge density PLL characteristics such as jit-
ter acquisition rate locking range etc are deterministic and
show minimal spread under various operating environments
The phase error processor also automatically puts the loop
in open-loop-mode when the incoming data stream contains
abnormal low edge rates When the PLL is in open-loop-
mode no update is made to the PLL’s filter variables in the
filter block The PLL can then use the pretrained frequency
and phase contents to perform data recovery Since the
loop is implemented digitally these values (the frequency
and phase variables) are retained The resolution of the fre-
quency variable is about 1 3 ppm of the incoming frequency
The resolution of the phase variable is about 40 ps
DIGITAL LOOP FILTER
The digital loop filter emulates a 1-pole 1-zero filter and
uses an automatic acquisition speed control circuit to dy-
namically adjust loop parameters
The digital loop filter takes the phase error indicator signals
Data Valid and Up Down from the Phase Error processor
and accumulates errors over a few cycles before passing on
the Data Valid and Up Down signals to the Phase Error to
Frequency converter
The filter has 4 sets of bandwidth and damping parameters
which are switched dynamically by an acquisition control
circuit The input Signal Detect (SD) starts the sequence
and thereafter no user programming is required to finish
the sequence
At the completion of the locking sequence the loop has the
narrowest bandwidth such that the loop produces minimal
recovered clock jitter The PLL can track an incoming fre-
quency offset of approximately
sition sequence the equivalent natural frequency of the
loop is reduced to about 7 kHz (
offset
The automatic tracking mechanism allows the loop to quick-
ly lock onto the initial data stream for data recovery (typical-
ly less than 10
clock jitter
PHASE ERROR TO FREQUENCY CONVERTER (O– F)
The Phase Error to Frequency Converter takes the Data
Valid and Up Down signals modified by the Digital Loop
Filter and converts them to triangle waves The frequency of
the triangle waves is then used to control the Frequency
Controlled Oscillator’s (FCO) 250 MHz oscillations
s) and yet produce very little recovered
g
200 ppm After the acqui-
g
56 ppm) of frequency
(Continued)
8
Each valid Up or Down signal causes a partial 7-bit counter
(using only 96 counts) to increment or decrement at the
When the Data Valid signal is not asserted the counter
holds count
The counter value is used to produce 3 triangle waves that
are offset in phase by 120 degrees This is done with a
special Pulse Density Modulator waveform synthesizer
which takes the place of a traditional Digital-Analog convert-
er The frequency of the triangle waves tells the Frequency
Controlled Oscillator how much to adjust oscillation The
phase relationships (leading or lagging) between the 3 sig-
nals indicates the direction of change
The minimum frequency of the triangle waves is 0 and cor-
responds to the case when the PLL is in perfect lock with
the incoming signal
The maximum frequency that the
duce determines the locking range of the PLL In this case
the maximum frequency of each triangle wave is 162 76
kHz which is produced when the
continuous count in one direction that is valid every
converter clock cycle of 15 625 MHz (250 MHz 16) The
triangle waves have an amplitude resolution of 48 digital
steps so a full rising and falling period takes 96 counts
which produces a maximum frequency of 162 76 kHz
(1 (1 15 625 kHz
The 96 digital counts of the triangle waves also lead to a
very fine PLL phase resolution of 42 ps (4 ns 96 counts)
This high phase resolution is achieved using very low fre-
quency signals in contrast to a standard PLL which must
operate at significantly higher frequencies than the data be-
ing tracked to achieve such high phase resolution
FREQUENCY CONTROLLED OSCILLATOR (FCO)
The frequency controlled oscillator produces a 250 MHz
clock that when divided by 2 is phase locked to the incom-
ing data’s clock
The FCO uses three 250 MHz reference clock signals from
the Clock Generation Module and three 0 Hz to 162 76 kHz
error clock signals from the Phase Error to Frequency Con-
verter as inputs Each signal in a triplet is 120 degrees
phase shifted from the next
Each corresponding pair (one 250 MHz and one error sig-
nal) of signals is mixed together using an amplitude switch-
ing modulator with the error signal modulating the refer-
ence All of the outputs are then summed together to pro-
duce the final 250 MHz
where f
– F converter’s clock rate of 15 625 MHz (250 MHz 16)
m
is the error frequency
96))
a
f
m
phase locked clock signal
– F converter can pro-
– F converter gets a
–F