DP83257VF National Semiconductor, DP83257VF Datasheet - Page 107

• Manufacturer Part Number: DP83257VF
• Description: IC FDDI LAYER CTRLR 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83257VF

• Controller Type: physical layer controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Interface: -
• Other names: *DP83257VF

LBC1
LBC2
LBC3
LBC4
LBC5
PH SEL
FBK IN
LSC
CLK16
XTAL IN
XTAL OUT
REF IN
REF SEL
LPFLTR
6 0 Signal Descriptions
CLOCK INTERFACE
The Clock Interface consists of 12 5 MHz and 25 MHz clocks supplied by the PLAYER
feedback inputs
Symbol
Pin
160
159
34
37
46
45
36
35
49
4
3
2
1
5
I O
O
O
O
O
O
I
I
I
I
I
Local Byte Clock TTL compatible 12 5 MHz 50% duty cycle clock outputs which are phase
locked to a crystal oscillator or reference signal The PH SEL input determines whether the five
phase outputs are phase offset by 8 ns or 16 ns
Phase Select TTL compatible input used to select either a 8 ns or 16 ns phase offset between the 5
local byte clocks (LBC’s) The LBC’s are phase offset 8 ns apart when PH SEL is at a logic LOW
level and 16 ns apart when at a logic HI level
Feedback Input TTL compatible input for use as the PLL’s phase comparator feedback input to
close the Phase Locked Loop This input is intended to be driven from one of the Local Byte Clocks
(LBC’s) from the same PLAYER
Local Symbol Clock TTL compatible 25 MHz output for driving the MACSI or BMAC devices This
output’s negative phase transition is aligned with the LBC1 output transitions and has a 40% HI and
60% LOW duty cycle
Clock 16 32 TTL compatible clock with a selectable frequency of approximately 15 625 MHz or
31 25 MHz The frequency can be selected using the Clock Select (CLKSEL) bit of the Mode 2
Register (MODE2)
Note No glitches appear at the output when switching frequencies
External Crystal Oscillator Input This input in conjunction with the XTAL OUT output is
designed for use of an external crystal oscillator network as the frequency reference for the clock
generation module’s internal VCO A diagram of the required circuit which includes only a 12 5 MHz
crystal and 2 loading capacitors is shown in Figure 3-19
This input is selected when the REF SEL input is at a logic LOW level When not being used this
input should be tied to ground
External Crystal Oscillator Output This output in conjunction with the XTAL IN input is designed
for use of an external crystal oscillator network as the frequency reference for the clock generation
module’s internal VCO A diagram of the required circuit which includes only a 12 5 MHz crystal and
2 loading capacitors is shown in Figure 3-19
Reference Input TTL compatible input for use as the PLL’s phase comparator reference frequency
This input is for use in dual attach station or concentrator configurations where there are multiple
PLAYER
This input is selected when the REF SEL input is at a logic HI level
Reference Select TTL compatible input which selects either the crystal oscillator inputs XTAL IN
and XTAL OUT or the REF IN inputs as the reference frequency inputs for the PLL
The crystal oscillator inputs are selected when REF SEL is at a logic LOW level and the REF IN
input is selected as the reference when REF SEL is at a logic HI level
Loop Filter This is a diagnostic output that allows monitoring of the clock generation module’s filter
node This output is disabled by default and does not need to be connected to any external device It
can be enabled using the FLTREN bit of the Clock generation module register (CGMREG)
Note In normal operation this pin should be disabled
a
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devices at a given site requiring synchronization
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device
Description
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device as well as reference and