DP83257VF National Semiconductor, DP83257VF Datasheet - Page 46

• Manufacturer Part Number: DP83257VF
• Description: IC FDDI LAYER CTRLR 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83257VF

• Controller Type: physical layer controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Interface: -
• Other names: *DP83257VF

Bit
D3
D4
D5
D6
D7
5 0 Registers
Symbol
CWI
LEMT
RCA
RCB
UDI
CONDITIONAL WRITE INHIBIT Set to 1 when bits within mentioned registers do not match bits in the
corresponding compare register This bit ensures that new (i e unread) data is not inadvertently cleared while old
data is being cleared through the Control Bus Interface
This bit is set to 1 to indicate that a bit in a condition write register was not written because it had changed since
the previous read The following registers are affected
Interrupt Condition Register (Register 02 ICR)
Current Transmit State Register (Register 04 CTSR)
Receive Condition Register A (Register 09 RCRA)
Receive Condition Register B (Register 0A RCRB)
CMT Condition Register (Register 20 CMTCR)
The previous registers are affected when they differ from the value of the corresponding bit in the following
registers respectively
Interrupt Condition Compare Register (Register 1A ICCR)
Current Transmit State Compare Register (Register 1B CTSCR)
Receive Condition Compare Register A (Register 1C RCCRA)
Receive Condition Compare Register B (Register 1D RCCRB)
CMT Condition Compare Register (Register 1F CMTCCR)
This bit must be cleared by software Note that this differs from the MACSI BMAC and BSI device bits of the same
name
The Configuration Register (Register 01 CR) can not be written to during scrubbing
LINK ERROR MONITOR THRESHOLD This bit is set to 1 when the internal 8-bit Link Error Monitor Counter
reaches zero It will remain set and is cleared by software
During the reset process (i e E RST
Error Monitor Counter is initialized to zero
RECEIVE CONDITION A This bit is set to 1 when
1 One or more bits in the Receive Condition Register A (RCRA) is set to 1 and
2 The corresponding mask bits in the Receive Condition Mask Register A (RCMRA) are also set to 1
In order to clear (i e set to 0) the Receive Condition A bit the bits within the Receive Condition Register A that are
set to 1 must first be either cleared or masked
RECEIVE CONDITION B This bit is set to 1 when
1 One or more bits in the Receive Condition Register B (RCRB) is set to 1 and
2 The corresponding mask bits in the Receive Condition Mask Register A (RCMRB) are also set to 1
In order to clear (i e set to 0) the Receive Condition B bit the bits within the Receive Condition Register B that are
set to 1 must first be either cleared or masked
USER DEFINABLE INTERRUPT This bit is set to 1 when one or any combination of the Sense Bits (SB0 SB1 or
SB2) in the User Definable Register (UDR) are set to 1
In order to clear (i e set to 0) the User Definable Interrupt Bit all Sense Bits must be set to 0
(Continued)
e
GND) the Link Error Monitor Threshold bit is set to 1 because the Link
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Description