DP83815CVNG National Semiconductor, DP83815CVNG Datasheet - Page 56

• Manufacturer Part Number: DP83815CVNG
• Description: IC CONTROLLER MEDIA ACCESS
• Manufacturer: National Semiconductor

Specifications of DP83815CVNG

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: PCI
• Voltage - Supply: 3.3V
• Current - Supply: 170mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83815CVNG

Subject to change without notice.
4.0 Register Set
4.2.14.1 Wake on LAN
The Wake on LAN logic provides several mechanisms for
bringing the DP83815 out of a low-power state. Wake on
ARP, Wake on Broadcast, Wake on Multicast Hash and
Wake on Phy Interrupt are enabled by setting the
corresponding bit in the Wake Command/Status Register,
WCSR. Before the hardware is programmed to a low
power state, the software must write a null receive
descriptor pointer to the Receive Descriptor Pointer
Register (RXDP) to ensure wake packets will be buffered in
the RX fifo. Please refer to the description of the RXDP
register for this procedure.
When a qualifying packet is received, the Wake on LAN
logic generates a Wake event and pulses the PMEN PCI
signal to request a Power Management state change. The
software must then bring the hardware out of low power
mode and, if the Power Management state was D3hot,
reinitialize Configuration Register space. A Wake interrupt
can also be generated which alerts the software that a
Wake event has occurred and a packet was received. The
software must then write a valid receive descriptor pointer
to RXDP. The incoming packet can then be transferred into
Bit
5
4
3
2
1
0
Bit Name
WKPAT0
WKMCP
WKUCP
WKARP
WKBCP
WKPHY
(Continued)
Wake on Pattern 0 match
Enable wake on match of pattern 0. R/W
Wake on ARP
Enable wake on ARP packet detection. R/W
Wake on Broadcast
Enable wake on broadcast packet detection. R/W
Wake on Multicast
Enable wake on multicast packet detection. R/W
Wake on Unicast
Enable wake on unicast packet detection. R/W
Wake on Phy Interrupt
Enable wake on Phy Interrupt. The Phy interrupt can be programmed for Link Change and a variety of
other Physical Layer events. R/W
56
host memory for processing. Note that the wake packet is
retained for processing - this is a feature of the DP83815.
In addition to the above Wake on LAN features, DP83815
also provides Wake on Pattern Matching, Wake on DA
match and Wake on Magic Packet
Wake on Pattern Matching
Wake on Pattern Matching is an extension of the Pattern
Matching feature provided by the Receive Filter Logic.
When one or more of the Wake on Pattern Match bits are
set in the WCSR, a packet will generate a wake event if it
matches the associated pattern buffer. The pattern count
and the pattern buffer memory are accessed in the same
way as in Pattern Matching for packet acceptance. The
minimum pattern count is 2 bytes and the maximum pattern
count is 64 bytes for patterns 0 and 1, and 128 bytes for
patterns 2 and 3. Packets are compared on a byte by byte
basis and bytes may be masked in pattern memory, thus
allowing for don’t cares. Refer to Section 4.2.18 Receive
Filter Logic for programming examples.
Description
Rev O

.
www.national.com