DP83815CVNG National Semiconductor, DP83815CVNG Datasheet - Page 74

• Manufacturer Part Number: DP83815CVNG
• Description: IC CONTROLLER MEDIA ACCESS
• Manufacturer: National Semiconductor

Specifications of DP83815CVNG

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: PCI
• Voltage - Supply: 3.3V
• Current - Supply: 170mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83815CVNG

4.0 Register Set
4.3.10 MII Interrupt Control Register
This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Link
State Change, Jabber Event, Remote Fault, Auto-Negotiation Complete or any of the counters becoming half-full. Note
that the TINT bit operates independently of the INTEN bit. In other words, INTEN does not need to be active to generate
the test interrupt.
4.3.11 MII Interrupt Status and Misc. Control Register
This register implements the MII Interrupt PHY Control and Status information. These Interrupts are PHY based events.
When any of these events occur and its respective bit is not masked, and MICR:INTEN is enabled, the interrupt will be
signalled in ISR:PHY.
Bit
8:0
15:2
15
14
13
12
11
10
Bit
9
1
0
Bit Name
MSK_LINK
MSK_ANC
MSK_RHF
MSK_JAB
MSK_FHF
Reserved
Bit Name
MSK_RF
Reserved
MINT
INTEN
TINT
Offset: 00C4h
Offset: 00C8h
(Continued)
Tag: MICR
Tag: MISR
MII Interrupt Pending: Default: 0, RO/COR
1 = Indicates that an interrupt is pending and is cleared by the current read.
0 = no interrupt pending
Mask Link: When this bit is 0, the change of link status event will cause the interrupt to be seen by the ISR.
Mask Jabber: When this bit is 0, the Jabber event will cause the interrupt to be seen by the ISR.
Mask Remote Fault: When this bit is 0, the Remote Fault event will cause the interrupt to be seen by the
ISR.
Mask Auto-Neg. Complete: When this bit is 0, the Auto-negotiation complete event will cause the inter-
rupt to be seen by the ISR.
Mask False Carrier Half Full: When this bit is 0, the False Carrier Counter Register half-full event will
cause the interrupt to be seen by the ISR.
Mask Rx Error Half Full: When this bit is 0, the Receive Error Counter Register half-full event will cause
the interrupt to be seen by the ISR.
Reserved: Default: 0, RO
Reserved: Writes ignored, Read as 0
Interrupt Enable:
1 = Enable event based interrupts
0 = Disable event based interrupts
Test Interrupt:
Forces the PHY to generate an interrupt at the end of each management read to facilitate interrupt testing.
1 = Generate an interrupt
0 = Do not generate interrupt
Access: Read Write
Access: Read Write
Size: 16 bits
Size: 16 bits
74
Description
Description
Hard Reset: 0000h
Hard Reset: 0000h
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