DP83916VF National Semiconductor, DP83916VF Datasheet - Page 80

• Manufacturer Part Number: DP83916VF
• Description: IC CTRLR ORIENT NETWK IN 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83916VF

• Controller Type: Network Interface Controller (NIC)
• Interface: Bus
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Operating Temperature: -
• Other names: *DP83916VF

7 0 AC and DC Specifications
MEMORY WRITE BMODE
Note 1 For successive read operations MWR remains low and for successive write operations MWR remains high During RBA and TBA transfers the MWR
signal will stay either high or low for the entire burst of the transfer During RDA and TDA transfers the MWR signal will switch on the rising edge of a Ti (idle) state
that is inserted between the read and the write operation
Note 2 Meeting the setup time for DSACK0 1 or STERM guarantees that the SONIC-16 will terminate the memory cycle 1
sampled or 1 cycle after STERM was sampled T2 states will be repeated until DSACK0 1 or STERM are sampled properly in a low state If the SONIC-16 samples
DSACK0 1 or STERM low during the T1 or first T2 state respectively the SONIC-16 will finish the current access in a total of two bus clocks instead of three
(assuming that programmable wait states are set to 0) DSACK0 1 are asynchronously sampled and STERM is synchronously sampled
Note 3 bcyc
Note 4 DS will only be asserted if the bus cycle has at least one wait state inserted
Number
T9
T10
T11a
T12a
T13a
T14
T15a
T18
T22
T30
T30a
T31
T31a
T36
T37
T39
T40
e
bus clock cycle time (T3) bch
BSCK to Address Valid
Address Hold Time from BSCK
BSCK to AS DS ECS Low
BSCK to AS ECS High
BSCK to DS High
AS Strobe Low Width (Note 3)
AS Strobe High Width (Note 3)
Write Data Strobe Low Width (Notes 3 4)
Address Valid to AS (Note 3)
DSACK0 1 Setup to BSCK (Note 2)
STERM Setup to BSCK (Note 2)
DSACK0 1 Hold from BSCK
STERM Hold from BSCK
BSCK to Memory Write Data Valid
BSCK to MRW (Write) Valid (Note 1)
Write Data Valid to Data Strobe Low (Note 3)
Memory Write Data Hold from BSCK
e
1 ASYNCHRONOUS MODE
e
Parameter
bus clock high time (T2)
(Continued)
80
bcyc
bcyc
bch
bcyc
bcyc
Min
12
12
10
5
8
6
b
b
b
b
b
18
15
40
7
5
20 MHz
bus clocks after DSACK0 1 were
Max
34
26
34
36
70
30
TL F 11722 – 67
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns