MC33889DWR2 Freescale Semiconductor, MC33889DWR2 Datasheet - Page 28

• Manufacturer Part Number: MC33889DWR2
• Description: IC SYSTEM BASE W/CAN 28-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MC33889DWR2

• Controller Type: System Basis Chip
• Interface: CAN
• Voltage - Supply: 5.5 V ~ 18 V
• Current - Supply: 45mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CAN WAKE-UP
wake-up cannot be disabled.
SPI WAKE-UP
mode. Wake-up is detected by the CS pin transition from a
low to high level. In stop mode this correspond to the
condition where the MCU and SBC are both in Stop mode,
and when the application wake-up events come through the
MCU.
SYSTEM POWER UP
DEVICE POWER UP, SBC WAKE UP
mode, the SBC enters into “reset mode” then into “normal
request mode”.
DEBUG MODE APPLICATION HARDWARE AND
SOFTWARE DEBUG WITH THE SBC.
board as the micro controller, it supplies both application
software and the SBC with a dedicated routine that must be
debugged. The following features allow the user to debug the
software by disabling the SBC internal software watchdog
timer.
DEVICE POWER UP, RESET PIN CONNECTED TO VDD1
SPI communication occurs to configure the device, a reset
occurs every 350 ms. In order to allow software debugging
and avoid an MCU reset, the Reset pin can be connected
directly to VDD1 by a jumper.
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33889
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
The device can wake-up from a CAN message. A CAN
The device can wake-up by the CS pin in sleep or stop
At power up the device automatically wakes up.
After device or system power up or a wake-up from sleep
When the SBC is mounted on the same printed circuit
At SBC power up, the VDD1 voltage is provided, but if no
W/D clear
SPI CS
WDOG
SPI
RESET
VDD1
Figure 10. Reset and WDOG Function Diagram
Watchdog
period
Watchdog register addressed
Watchdog timeout
BATTERY FALL EARLY WARNING
voltage is below the 6.1 V typical. This interrupt is maskable.
A hysteresis is included. Operation is only in Normal and
Stand-by modes. VBAT low state reports in the IOR register.
RESET AND WDOG OPERATION
operations. Reset is active at device power up and wake-up.
Reset is activated in case the VDD1 falls or the watchdog is
not triggered. The WDOG output is active low as soon as the
reset goes low and stays low for as long as the watchdog is
not properly re-activated by the SPI.
drive external components of the application, for instance to
signal the MCU is in a wrong operation. Even if it is internally
turned on (low-state), the reset pin can be forced to 5.0 V at
25°C only, thanks to its internally limited current drive
capability. The WDOG stays low until the Watchdog register
is properly addressed through the SPI.
DEBUG MODES WITH SOFTWARE WATCHDOG
DISABLED THOUGH SPI (NORMAL DEBUG, STANDBY
DEBUG AND STOP DEBUG)
In order to avoid unwanted watchdog disables, and to limit the
risk of disabling the watchdog during an SBC normal
operation, the watchdog disable has to be performed with the
following sequence:
SBC enters normal request mode)
Normal mode
enables the debug mode). (Complete SPI byte: 000 1 0000)
The following figure shows the reset and watchdog output
The WDOG output pin is a push pull structure than can
This function provides an interrupt when the VSUP
The software watchdog can be disabled through the SPI.
Step 1) Power down the SBC
Step 2) Power up the SBC (The BATFAIL bit is set, and the
Step 3) Write to the TIM1 register to allow the SBC to enter
Step 4) Write to the MCR register with data 0000 (this
Analog Integrated Circuit Device Data
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