ADM8513X-AD-T-1 Infineon Technologies, ADM8513X-AD-T-1 Datasheet
ADM8513X-AD-T-1
Specifications of ADM8513X-AD-T-1
ADM8513XADT1XP
SP000077769
Available stocks
Related parts for ADM8513X-AD-T-1
ADM8513X-AD-T-1 Summary of contents
Page 1
...
Page 2
... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
Page 3
... ISAC , ITAC ® ® ® QUAT , QuadFALC , SCOUT ® ® 10BaseV , 10BaseVX are registered trademarks of Infineon Technologies AG. 10BaseS™, EasyPort™, VDSLite™ are trademarks of Infineon Technologies AG. Microsoft ® Corporation, Linux of Linus Torvalds, Visio Incorporated. ® ® ® , ASP , DigiTape , DuSLIC ® ...
Page 4
Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
Get Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
List of Figures Figure 1 Pin Diagram 11 Figure 2 Block Diagram 15 Figure 3 Packet Form when Receive 17 Figure 4 Packet Form when Transmit 18 Figure 5 EEPROM Interface Timing 77 Figure 6 Package 80 Figure 7 Placement ...
Page 7
List of Tables Table 1 Abbreviations for Pin Type 11 Table 2 Abbreviations for Buffer Type 12 Table 3 Host Interface 12 Table 4 Physical Interface 13 Table 5 LED Interface 13 Table 6 Mapping between LED action and EEPROM ...
Page 8
Table 50 Data Stage 23 Table 51 Setup Stage 23 Table 52 Data Stage 23 Table 53 Setup Stage 23 Table 54 Data Stage 24 Table 55 Setup Stage 24 Table 56 Data Stage 24 Table 57 Setup Stage 24 ...
Page 9
... Product Overview 1.1 Package Information Product Name Product Type ADM8513 ADM8513-AD-T-1 ADM8513X ADM8513X-AD-T-1 1) “x” stands as key to Infineon packing variants, such as “Tape&reel, drypacked” as well as for the environmentally “green” package version. 1.2 Features Main features: • Industrial Standard – IEEE 802.3/802.3u 10Base-T/100Base-Tx compliant. ...
Page 10
Mode 0: Resume by remote wakeup or host when OS goes into standby – Mode 1: Resume by host when OS goes into standby. • Miscellaneous – Supports 6 GPIO pins – Provides 48-pin LQFP package – 3.3 V ...
Page 11
Interface Description 2.1 Pin Assignment Diagram Pin Diagram ADM8513/X. VDD33 EECS EESK EEDI EEDO VDD33 Vss GPIO1 GPIO0 POREN# NC Vss Figure 1 Pin Diagram 2.2 Pin Description by Function Table 1 Abbreviations for Pin Type Abbreviations Description I ...
Page 12
Table 1 Abbreviations for Pin Type (cont’d) Abbreviations Description NU Not Usable (JEDEC Standard) NC Not Connected (JEDEC Standard) Table 2 Abbreviations for Buffer Type Abbreviations Description Z High impedance PU1 Pull up, 10 kΩ PD1 Pull down, 10 kΩ ...
Page 13
Table 4 Physical Interface Pin or Ball Name No. 86, 35 RXIP, RXIN 46, 47 TXOP, TXON 44 CLK25_I 43 CLK25_O 41 RIBB 38, 39 TSTA, TSTB 2.2.3 LED Interface Table 5 LED Interface Pin or Ball Name No. 33 ...
Page 14
EEPROM Interface Table 7 EEPROM Interface Pin or Ball Name No. EECS 2 EEDI 4 EEDO 5 EESK 3 2.2.5 Miscellaneous Table 8 Miscellaneous Pin or Ball Name No. 9 GPIO5 8 GPIO4 24 GPIO3 26 GPIO2 27 GPIO1 ...
Page 15
Table 9 Power USB Pin or Ball Name No. 21 UVDD 33 18 UVSS 2.2.7 POWER Table 10 Power Pin or Ball Name No 13, 22, VDD 12, 23, 17, VSS 25 VAARef ...
Page 16
Function Description 3.1 USB Interface USB is a likely solution any time you want to use a computer to communication with devices outside the computer. The interface is suitable for one-of-kind and small-scale designs as well as mass-produced, standard ...
Page 17
Endpoint 1 Bulk IN Endpoint charge of sending the received Ethernet packet to USB host. An Ethernet packet will be split to multiple 64 bytes USB packets on USB. The end of the Ethernet packet is ...
Page 18
Table 12 USB Packet Format Field 1st Byte in 1st USB Packet Content len[7:0]: Low byte Ethernet packet length USB Packet Figure 4 Packet Form when Transmit 4.2.2 Endpoint 3 Interrupt IN Endpoint charge ...
Page 19
Table 16 Data Stage Offset0(1B) {RegIndex} The returned total number of registers depends on the length field. 5.1.2 Set Register (Vendor Specific) Burst Write Table 17 Setup Stage bmReq bReq wValue(2B) wIndexLow(1B) wIndexHigh(1B) wLength L(1B) wLength H(1B ...
Page 20
Table 23 3rd OUT Transfer Offset0(1B) Offset1(1B 5.1.3 Get Status (Device) Table 24 Setup Stage bmReq bReq 80 0 Table 25 Data Stage D[15:2] 0 5.1.4 Get Status (Interface) Table 26 Setup Stage bmReq bReq 81 0 Table ...
Page 21
Table 30 Setup Stage bmReq bReq 82 0 Table 31 Data Stage D[15:1] 0 5.1.7 Get Status (EP2) Bulk OUT Table 32 Setup Stage bmReq bReq 82 0 Table 33 Data Stage D[15:1] 0 5.1.8 Get Status (EP3) Interrupt IN ...
Page 22
Table 37 Data Stage: wLength Field Specifies the Total byte Count to Return 1 Offset 0 Offset 1 Offset 2 (USB (type) release no. L) 12(1 ) 01 Table 38 Data Stage: wLength Field ...
Page 23
Table 44 EP1 Descriptor Offset 0 Offset 1 Offset 2 (Length) (DscrType) (EPAddr) 07(1 ) 05 Table 45 EP2 Descriptor Offset 0 Offset 1 Offset 2 (Length) (DscrType) (EPAddr) 07(1 ) 05 ...
Page 24
Get Descriptor (String) Index 2, Product Table 51 Setup Stage BmReq bReq 80 06 Table 52 Data Stage Offset 0 (Length) length 5.1.14 Get Descriptor (String) Index 3, Serial No. Table 53 Setup Stage BmReq bReq 80 ...
Page 25
Table 58 Data Stage Offset0 (AltIntf) (1B) 00 5.1.17 Clear Feature (Device) Remote Wakeup Table 59 Setup Stage BmReq bReq 00 01 5.1.18 Set Feature (Device) Remote Wakeup Table 60 Setup Stage BmReq bReq 00 03 5.1.19 Clear Feature (EP ...
Page 26
Registers Description 6.1 System Registers Table 63 Registers Address Space Module Base Address System Registers 0000 0000 Table 64 Registers Overview Register Short Name Register Long Name Res30_Res155 Reserved 30~Reserved 155 EC0 Ethernet Control 0 EC1 Ethernet Control 1 ...
Page 27
Table 64 Registers Overview (cont’d) Register Short Name Register Long Name Res8 Reserved 8 Res9 Reserved 9 Res10 Reserved 10 EEPROMO EEPROM Offset EEPROMDL EEPROM Data Low EEPROMDH EEPROM Data High EEPROMAC EEPROM Access Control Res11 Reserved 11 PHYA PHY ...
Page 28
Table 64 Registers Overview (cont’d) Register Short Name Register Long Name Res16 Reserved 16 Res17 Reserved 17 WUF1M_0 Wakeup Frame 1 Mask WUF1M_1 Wakeup Frame 1 Mask 1 WUF1M_2 Wakeup Frame 1 Mask 2 WUF1M_3 Wakeup Frame 1 Mask 3 ...
Page 29
Table 64 Registers Overview (cont’d) Register Short Name Register Long Name WUF2M_15 Wakeup Frame 2 Mask 15 WUF2O Wakeup Frame 2 Offset WUF2CRCL Wakeup Frame 2 CRC Low WUF2CRCH Wakeup Frame 2 CRC High Res23 Reserved 23 Res24 Reserved 24 ...
Page 30
Table 65 Register Access Types (cont’d) Mode Symbol Description HW Interrupt high, ihsc Differentiates the input signal (low- self clearing >high) register cleared on read Interrupt low, ilsc Differentiates the input signal (high- self clearing >low) register cleared on read ...
Page 31
Field Bits Type SBO 2 rw RXMA 1 rw RXCS 0 rw Ethernet Control 1 EC1 Ethernet Control 1 Field Bits Type Res 7 10M MII 2 r Res 1:0 ro ...
Page 32
Ethernet Control 2 EC2 Ethernet Control 2 Field Bits Type MEPL 7 rw Res 6 ro LEEPRS 5 rw EEPRW PROM 2 rw RXBP 1 rw EP3RC 0 rw Data Sheet Offset 02 H Description ...
Page 33
Reserved 0 Res0 Reserved 0 Field Bits Type Res 7:0 ro Similar Registers Table 67 Reserved Registers Register Short Name Register Long Name Res1 Reserved 1 Res2 Reserved 2 Res3 Reserved 3 Res4 Reserved 4 Res5 Reserved 5 Res6 Reserved ...
Page 34
Table 67 Reserved Registers (cont’d) Register Short Name Register Long Name Res26 Reserved 26 Res27 Reserved 27 Res28 Reserved 28 Res29 Reserved 29 Res30_Res155 Reserved 30~Reserved 155 Multicast Address 0 MA0 Multicast Address 0 Field Bits Type MAB0 7:0 rw ...
Page 35
Multicast Address 2 MA2 Multicast Address 2 Field Bits Type MAB2 7:0 rw Multicast Address 3 MA3 Multicast Address 3 Field Bits Type MAB3 7:0 rw Data Sheet Offset 0A H Description Multicast 2 Multicast address byte [23:16] Offset 0B ...
Page 36
Multicast Address 4 MA4 Multicast Address 4 Field Bits Type MAB4 7:0 rw Multicast Address 5 MA5 Multicast Address 5 Field Bits Type MAB5 7:0 rw Data Sheet Offset 0C H Description Multicast 4 Multicast address byte [39:32] Offset 0D ...
Page 37
Multicast Address 6 MA6 Multicast Address 6 Field Bits Type MAB6 7:0 rw Multicast Address 7 MA7 Multicast Address 7 Field Bits Type MAB7 7:0 rw Data Sheet Offset 0E H Description Multicast 6 Multicast address byte [55:48] Offset 0F ...
Page 38
Ethernet ID 0 EID0 Ethernet ID 0 Field Bits Type EID0 7:0 rw Ethernet ID 1 EID1 Ethernet ID 1 Field Bits Type EID1 7:0 rw Data Sheet Offset 10 H Description Ethernet ID 0 The 1st byte of Ethernet ...
Page 39
Ethernet ID 2 EID2 Ethernet ID 2 Field Bits Type EID2 7:0 rw Ethernet ID 3 EID3 Ethernet ID 3 Field Bits Type EID3 7:0 rw Data Sheet Offset 12 H Description Ethernet ID 2 The 3rd byte of Ethernet ...
Page 40
Ethernet ID 4 EID4 Ethernet ID 4 Field Bits Type EID4 7:0 rw Ethernet ID 5 EID5 Ethernet ID 5 Field Bits Type EID5 7:0 rw Data Sheet Offset 14 H Description Ethernet ID 4 The 5th byte of Ethernet ...
Page 41
Pause Timer PT Pause Timer Field Bits Type PT 7:0 rw Receive Packet Number Based Flow Control RPNBFC Receive Packet Number Based Flow Control Field Bits Type PN 6:1 rw FCP 0 rw Data Sheet Offset 18 H Description Pause ...
Page 42
Occupied Receive FIFO Based Flow Control ORFBFC Occupied Receive FIFO Based Flow Control Field Bits Type RXS 6:1 rw FCRXS 0 rw EP1 Control EP1C EP1 Control Field Bits Type EP1S0E 7 rw FID 6:5 rw Data Sheet Offset 1B ...
Page 43
Field Bits Type FI 4:0 rw EEPROM Offset EEPROMO EEPROM Offset Field Bits Type ROMO 5:0 rw EEPROM Data Low EEPROMDL EEPROM Data Low Field Bits Type ROMDL 7:0 rw EEPROM Data High EEPROMDH EEPROM Data High Data Sheet Description ...
Page 44
Field Bits Type ROMDH 7:0 rw Data Sheet Description ROM Data High EEPROM Write: The data set in this register will be written to EEPROM EEPROM Read: The data read from EEPROM will be stored in this register 44 ADM8513 ...
Page 45
EEPROM Access Control EEPROMAC EEPROM Access Control Field Bits Type RDE 1 rw WRE 0 rw PHY Address PHYA PHY Address Field Bits Type PHYA 4:0 rw Data Sheet Offset 23 H Description Done Set by HW ...
Page 46
PHY Data Low PHYDL PHY Data Low Field Bits Type PHYDL 7:0 rw PHY Data High PHYDH PHY Data High Field Bits Type PHYDH 7:0 rw Data Sheet Offset 26 H Description PHY Data Low SW set this register when ...
Page 47
PHY Access Control PHYAC PHY Access Control Field Bits Type RDPHY 6 rw WRPHY 5 rw PHYRA 4:0 rw USB Bus Status USBBS USB Bus Status Field Bits Type USBR 1 rw USBS 0 rw Transmit Status ...
Page 48
TS1 Transmit Status 1 Field Bits Type TXUE JTO 2 r Data Sheet Offset 2B H Description TX Underrun Error Set indicate tx ...
Page 49
Transmit Status 2 TS2 Transmit Status 2 Field Bits Type TXFF 7 r TXFE 6 r TXPC 3:0 r Receive Status RS Receive Status Field Bits Type RXP 1 r RXO 0 r Data Sheet Offset 2C H Description TX ...
Page 50
Receive Lost Packet Count High RLPCH Receive Lost Packet Count High Field Bits Type RPL 7 r RXLPC 6:0 r Receive Lost Packet Count Low RLPCL Receive Lost Packet Count Low Field Bits Type RXLPC 7:0 r Wakeup Frame 0 ...
Page 51
Field Bits Type F0M 7:0 rw Similar Registers Table 68 Wakeup Frame 0 Mask Registers Register Short Name Register Long Name WUF0M_1 Wakeup Frame 0 Mask 1 WUF0M_2 Wakeup Frame 0 Mask 2 WUF0M_3 Wakeup Frame 0 Mask 3 WUF0M_4 ...
Page 52
Wakeup Frame 0 CRC Low WUF0CRCL Wakeup Frame 0 CRC Low Field Bits Type F0CRCL 7:0 rw Wakeup Frame 0 CRC High WUF0CRCH Wakeup Frame 0 CRC High Field Bits Type F0CRCH 7:0 rw Data Sheet Offset 41 H Description ...
Page 53
Wakeup Frame 1 Mask WUF1M_0 Wakeup Frame 1 Mask Field Bits Type F1M 7:0 rw Similar Registers Table 69 Wakeup Frame 1 Mask Registers Register Short Name Register Long Name WUF1M_1 Wakeup Frame 1 Mask 1 WUF1M_2 Wakeup Frame 1 ...
Page 54
Field Bits Type F1O 7:0 rw Data Sheet Description Offset for Wakeup Frame 1 54 ADM8513 Data Sheet Registers Description Rev. 1.21, 2005-12-05 ...
Page 55
Wakeup Frame 1 CRC Low WUF1CRCL Wakeup Frame 1 CRC Low Field Bits Type 7:0 rw Wakeup Frame 1 CRC High WUF1CRCH Wakeup Frame 1 CRC High Field Bits Type F1CRCH 7:0 rw Data Sheet Offset 59 H Description The ...
Page 56
Wakeup Frame 2 Mask WUF2M Wakeup Frame 2 Mask Field Bits Type F2M 7:0 rw Similar Registers Table 70 Wakeup Frame 2 Mask Registers Register Short Name Register Long Name WUF2M_1 Wakeup Frame 2 Mask 1 WUF2M_2 Wakeup Frame 2 ...
Page 57
Field Bits Type F2O 7:0 rw Data Sheet Description Offset for Wakeup Frame 2 57 ADM8513 Data Sheet Registers Description Rev. 1.21, 2005-12-05 ...
Page 58
Wakeup Frame 2 CRC Low WUF2CRCL Wakeup Frame 2 CRC Low Field Bits Type F2CRCL 7:0 rw Wakeup Frame 2 CRC High WUF2CRCH Wakeup Frame 2 CRC High Field Bits Type F2CRCH 7:0 rw Data Sheet Offset 71 H Description ...
Page 59
Wakeup Control WUC Wakeup Control Field Bits Type EMP 7 rw ELS 6 rw EWF0 5 rw WUF1 4 rw WUF2 3 rw CRC16 2 rw Data Sheet Offset 78 H Description Enable Magic Packet Set enable ...
Page 60
Wakeup Status WUS Wakeup Status Field Bits Type RXMP RXWF Internal PHY Control IPHYC Internal PHY Control Field Bits Type EPHY 1 rw Data Sheet Offset 7A H Description Receives ...
Page 61
Field Bits Type PHYR 0 rw GPIO[5:4] Control GPIO54C GPIO[5:4] Control Field Bits Type G5OE 5 rw G5OV 4 rw G5IV 3 r G4OE 2 rw G4OV 1 rw G4IV 0 r Data Sheet Description Internal PHY Reset The internal ...
Page 62
GPIO[1:0] Control GPIO10C GPIO[1:0] Control Field Bits Type G1OE 5 rw G1OV 4 rw G1IV 3 r G1OE 2 rw G0OV 1 rw G0IV 0 r Data Sheet Offset 7E H Description GPIO1 Output Enable 0 IN, GPIO1 is used ...
Page 63
GPIO[3:2] Control GPIO32C GPIO[3:2] Control Field Bits Type G3OE 5 rw G3OV 4 rw G3IV 3 r G2OE 2 rw G2OV 1 rw G2IV 0 r Data Sheet Offset 7F H Description GPIO3 Output Enable 0 IN, GPIO3 is used ...
Page 64
TEST Test TEST Field Bits Type Res 7:0 ro Test Mode TM Test Mode Field Bits Type Res 7:0 ro 6.2 PHY Registers Description Table 71 Registers Address SpaceRegisters Address Space Module Base Address System Registers 0000 0000 Table 72 ...
Page 65
Table 72 Registers Overview (cont’d) Register Short Name Register Long Name ANLPA Auto-Negotiation Link Partner Ability ANE Auto-Negotiation Expansion The register is addressed wordwise. Table 73 Register Access Types Mode Symbol Description HW read/write rw Register is used as input ...
Page 66
Table 74 Registers Clock DomainsRegisters Clock Domains Clock Short Name 6.2.1 PHY Registers Data Sheet Description 66 ADM8513 Data Sheet Registers Description Rev. 1.21, 2005-12-05 ...
Page 67
Control CTL Control Field Bits Type RST 15 rwsc ANE ISO rwsc Self Clearing Reset Reset this port ...
Page 68
Reset the registers to their default values. Note that this does not affect registers 20, 22 31. These registers are not reset by this bit to allow test configurations to be written and then not affected by ...
Page 69
Field Bits Type 10HD 11 ro 100TFD 10 ro 100THD 9 ro MFPS 6 ro ANC ro, lh ANA ro ro Note: Jabber Detect Only ...
Page 70
PHY Identifier 1 PHYI1 PHY Identifier 1 Field Bits Type PHYI 15:0 ro PHY Identifier 2 PHYI2 PHY Identifier 2 Field Bits Type PHYI1 15:10 ro PHYI2 9:4 ro PHYI3 3:0 ro Note: This uses the OUI of Infineon-ADMtek, device ...
Page 71
Auto-Negotiation Advertisement ANA Auto-Negotiation Advertisement Field Bits Type 12:11 ro PAU 100FD 8 rw 100HD 7 rw 10FD 6 rw 10HD 4:0 ro Data Sheet ...
Page 72
Auto-Negotiation Link Partner Ability The register is used to view the advertised capabilities of the link partner once auto negotiation is complete. The contents of this register should not be relied upon unless register 1 bit 5 is set (auto ...
Page 73
Field Bits Type LPNP 3 ro NPA ro, lh LPAN 0 ro Data Sheet Description Link Partner Next Page Able 0 NNP, Link Partner is not Next Page Able B 1 NP, Link Partner is Next ...
Page 74
Electrical Characteristics 7.1 Absolute Maximum Ratings Table 75 Absolute Maximum Rating Parameter Symbol V Supply Voltage Input Voltage Output Voltage OUT P Power Consumption C T Storage Temperature STG T Operation Temperature AMB ...
Page 75
Table 77 USB Interface DC Specification (cont’d) Parameter Differential Common Mode Range Output High Voltage Output Low Voltage Output Signal Crossover Voltage 8 EEPROM Interface DC Specification 8.1 Recommended Operating Conditions Table 78 EEPROM Interface DC Specification Parameter Input High ...
Page 76
Reset Timing ADM8513/X can be reset either by hardware, software or USB reset. • A hardware reset is accomplished by asserting the RST# pin after powering up the device. It should have a duration of at least 100 ms ...
Page 77
EECS EESK EEDI EEDO Figure 5 EEPROM Interface Timing 10 EEPROM Interface & Example If the EEPROM contents from offset 0 to offset 5 is “FF_FF_FF_FF_FF_FF”, the EEPROM isn't programmed correctly. The default values for every field are used instead ...
Page 78
Table 82 EEPROM Interface (cont’d) Offset(Byte) Field Description 12 ProID_lo The low byte of product ID. 13 ProID_hi The high byte of product ID. 14 Manu_str_len The length for manufacture string. 15 Manu_str_offset The word offset address of manufacture string. ...
Page 79
Table 83 EEPROM Example (cont’d) Offset(Byte) Value Description 16 1E product string length 1E bytes 17 18 product string starts from word offset 18h, thus byte offset serial number string length 0A bytes 19 38 serial number ...
Page 80
Package Figure 6 Package Data Sheet 80 ADM8513 Data Sheet Package Rev. 1.21, 2005-12-05 ...
Page 81
Note: This diagram has a 32pin. But, the relative parameters presents 48pin package data. So, please ignore the pin number and regard the diagram as 48pin. Make an example: Parameter “E” (9mm) means the distance between the two opposite sides. ...
Page 82
Table 84 Dimensions for 48 Pin LQFP Package Symbol Millimeter (mm) Min. A – 0.08 1 Θ 0° Θ 0° 1 Θ 11° 2 ...
Page 83
Table 84 Dimensions for 48 Pin LQFP Package (cont’d) Symbol Millimeter (mm aaa bbb ccc ddd Data Sheet 0.50 BSC. 5.50 5.50 Tolerance of Form and Position 0.20 0.20 0.08 0.08 83 ADM8513 Data Sheet ...
Page 84
Appendix Layout Guide Placement: • At USB side, place ADM8513/X and USB connector as close as possible. • At Ethernet side, place ADM8513/X, transformer and RJ45 as close as possible. • The crystal or OSC device should be closed ...
Page 85
Trace routing • Keep USB differential pair data signal D+ and D-: – Trace width should be as wide as possible. – Make D+ and D- traces route at the same signal plane and not pass through the other plane. ...
Page 86
Figure 11 Trace Routing 3 • Vcc trace should be short and prefer route in the format of the plane a special for GND. Power and Ground • All of the Vcc pin should have a 0.1uF SMD capacitors which ...
Page 87
Please connect 10K Ohm Ribb resistance gnd, pin40(GndRef) and pin37(GndR) first then use signal via to Gnd (Specially for 2 layers board design). Bad Figure 14 Power and Ground 3 Data Sheet Good 87 ADM8513 Data Sheet Appendix Layout ...
Page 88
... Published by Infineon Technologies AG ...