CS8952-IQZ Cirrus Logic Inc, CS8952-IQZ Datasheet
CS8952-IQZ
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CS8952-IQZ Summary of contents
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... RXD[3:0] RX_CLK RX_EN http://www.cirrus.com Description The CS8952 uses CMOS technology to deliver a high- performance, low-cost 100BASE-X/10BASE-T Physical Layer (PHY) line interface. It makes use of an adaptive equalizer optimized for noise and near end crosstalk (NEXT) immunity to extend receiver operation to cable lengths exceeding 160 m. In addition, the transmit cir- cuitry has been designed to provide extremely low transmit jitter (< ...
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... MII Management Frame Structure ................................................................ 28 5. CONFIGURATION .................................................................................................. 29 5.1 Configuration At Power-up/Reset Time......................................................... 29 5.2 Configuration Via Control Pins ...................................................................... 29 5.3 Configuration via the MII ............................................................................... 29 6. CS8952 REGISTERS .............................................................................................. 30 7. DESIGN CONSIDERATIONS .................................................................................. 62 7.1 Twisted Pair Interface ................................................................................... 62 7.2 100BASE-FX Interface.................................................................................. 62 7.3 Internal Voltage Reference ........................................................................... 63 7.4 Clocking Schemes ........................................................................................ 63 7 ...
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... Except Supply Pins Power Applied (AVSS, DVSS = 0 V, all voltages with respect Symbol Core V DD MII V DD_MII MHz quartz crystal is used, it must meet the fol- Min - -50 - CS8952 Min Max Unit -0.3 6.0 V -0.3 6.0 - +/-10 -55 +125 °C -65 +150 ° ...
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... IXH I -40 IXL I IXH 39.996 IXC t IXL (Note 1) I DDHPDN (Note 1) I DDSPDN (Note 1) I DDSLPUP 4.0mA 10.0mA 4.0mA OL = 43.0mA OL = 26.0mA 4.0mA -4.0mA -4.0mA OH = -20.0mA OH = -20.0mA OH CS8952 Typ Max - 0.5 3.5 - VDD+0 40.004 135 145 - 900 - - 900 - - - 0.4 2 2.4 ...
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... CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 (CONTINUED) (Over recommended operating conditions) Symbol Min -4.0mA 20 0.0V -20 I -3800 LEAK 0<=V<=V -10 DD CS8952 Typ Max - - - - 0 1/3 V DD_MII - 20% - 2/3 V DD_MII DD_MII - 20 DD_MII - - - - - - 200 - - 20 - +10 Unit µA µA µA 5 ...
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... Symbol ISQ V SQL t TTX1 t TTX2 t TTX3 t TRX1 t TRX2 t LN1 t LN2 t LN3 t LN4 t LN5 t LN6 t TTX1 t RTX1 t t RTX3 RTX4 t t LN1 LN2 t LN4 t LN6 CS8952 Min Typ Max 2.2 - 2.8 300 - 525 125 - 290 - - 4.5 250 - - - - +/-13 +/-13 200 150 50 52 150 ...
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... DS206F1 Symbol Min V 0. SYM t 3 RFS t - DCD OUT - 0 -1.830 1 V -1.035 -1.830 3 V -1.035 CMIP RX/TX Signaling for 100Base- RX_NRZ+/- CS8952 Typ Max - 1.05 - 102 - 5.0 - 0.5 - +/-0 400 1400 100 - ohms - 1 1000 - 350 - -1.605 - -0.880 - 1.6 - -1.605 - -0.880 3. Unit p-p ...
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... Start of RX+/- Stream t CRS t COL RX_EN RX_DV RXD[3:0], RX_ER/RXD4 RX_CLK CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 Symbol WL Aligned t DLAT 5B Aligned t CRS1 t CRS2 t COL1 t COL2 DIS End of Stream CRS1 COL1 RLAT CS8952 Min Typ Max - TBD - - TBD - t CRS2 t COL2 t DIS Unit ...
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... RXD[4:0] setup to rising edge of RX_CLK RXD[4:0] hold after rising edge of RX_CLK Start of 5B symbol to symbol output on RX[4:0] RX Symbol RX+/- 0 RXD[4:0], RX_CLK CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 Symbol WL RLAT 5B Mode RX Symbol RX Symbol N N RLAT Data RX Data CS8952 Min Typ Max - OUT 1 OUT Unit ...
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... SU2 TX_EN t SU1 TXD[3:0], Data TX_ER/TXD4 IN t CRS1 CRS TX+/- CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 Symbol t SU1 t SU2 t HD1 t HD2 t HD3 t CRS1 t CRS2 t LAT t HD2 t HD1 t LAT Symbol Out CS8952 Min Typ Max Input/Output Input Input t CRS2 Output Output Unit ...
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... TXD[4:0] Hold after TX_CLK High TX_ER Hold after TX_CLK High TXD[4:0] Sampled to TX+/- output (TX Latency) TX_CLK t t SU1 HD1 Data TXD[4: LAT TX+/- CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 Symbol Min t 10 SU1 t HD1 t HD2 t LAT Symbol OUT CS8952 Typ Max - - Input/Output Input Output Unit ...
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... RX_EN de-asserted to RX_DV, RXD[3:0]. RX_ER in high impedance state RX+/- t CRS t COL RX_EN RX_DV RXD[3:0], RX_ER RX_CLK CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 Symbol WL RLAT t CRS1 t CRS2 t COL1 t COL2 DIS CRS1 COL1 RLAT CS8952 Min Typ Max - 400 - - 200 - 2 CRS2 t COL2 t DIS Unit ...
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... TX_CLK COL CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 Symbol t SU1 t SU2 t SU3 t HD1 t HD2 t HD3 t CRS1 t CRS2 t LAT t COL t COLP 10BASE-T Transmit Timing t LAT Valid Data SQE Timing t SQE t SQEP CS8952 Min Typ Max 0.65 0.9 1.6 0.65 1.0 1.6 ...
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... RX_CLK hold after CRS off RXD[0] throughput delay CRS turn off delay RX+/- t CRS CRS RX_CLK RXD[0] CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 Symbol Min t DATA t CRS t RDS t RDH t RCH CRSOFF DATA CS8952 Typ Max - - 1200 - - 600 250 - - 400 t t RCH CRSOFF Unit ...
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... Transmit throughput delay TX_CLK t EHCH TX_EN t DSCH TXD[0] t STUD TX+/- CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 Symbol Min t 10 EHCH t 10 CHEL t 10 DSCH t 10 CHDU t - STUD t - TPD t PD Valid Data CS8952 Typ Max Unit - - 500 ns - 500 ns Input/Output t CHEL Input t CHDU Input Output 15 ...
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... Clock pulse to clock pulse TX+/- Clock Pulse TX+/- CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 Symbol t BTB t FLPW - CTD t CTC t FLPW t BTB Data Pulse t PW CTD CTC CS8952 Min Typ Max 100 - 55.5 64 69.5 111 128 139 Clock Pulse Unit ms ms ea. ns µs µs 16 ...
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... MDIO Hold after MDC (MDIO as input) MDC to MDIO valid (MDIO as output) CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 Symbol Min WL MD1 t MD2 t MD3 DIRECTION OUT of chip MDC t t MD1 MD2 MDIO Valid Data Valid Data t MD3 MDIO Valid Data CS8952 Typ Max OUT Unit ...
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... CS8952 provides a 10BASE-T serial port (Seven-wire ENDEC inter- face). 2.4 Typical Connection Diagram Figure 1 illustrates a typical MII to CS8952 appli- cation with twisted-pair and fiber interfaces. Refer CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 to the Analog Design Considerations section for ...
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... RX_NRZ- RX_NRZ+ 130 Ω TXSLEW0 NC TXSLEW1 NC AN0 NC AN1 NC TCM VSS TEST0 TEST1 7 21 Figure 1. Typical Connection Diagram CS8952 0.1 µF 49.9 Ω 51 Ω 75 Ω 51 Ω 51 Ω 51 Ω 75 Ω 51 Ω 51 Ω 0.1 µF 0.01 µF 2KV +5 V 0.1 µF 130 Ω 0.1 µF 191 Ω ...
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... CS8952, eliminating the need for the system to poll the CS8952 for state changes. The RX_EN signal allows the receiver outputs to be electrically isolated. The ISODEF pin controls the value of register bit ISOLATE in the Basic Mode Control Register (address 00h) which in turn electrically isolates the CS8952's MII data path ...
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... CS8952 Comments Comments This portion of the table relates received 5-bit symbols to received 4-bit nibbles only. The control code groups may not be transmitted in the data portion of the frame. ...
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... BP4B5B can be selected by set- Function ting bit 14 of the same register. Pin BPALIGN causes more of the CS8952 to be bypassed than the BP4B5B pin. BPALIGN also by- passes the scrambler/descrambler, and the NRZI to NRZ converters (see Figure 1). Also, for repeater applications, pin REPEATER should be asserted to redefine the function of the CRS (carrier sense) pin ...
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... MII register bits. (See Ta- ble 5). 3.1.3.2 Collision Detection If half duplex operation is selected, the CS8952 de- tects a 10BASE-T collision whenever the receiver and transmitter are active simultaneously. When a collision is present, the collision is reported on pin COL. Collision detection is undefined for full-du- plex operation ...
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... Ethernet link segment to share infor- mation and automatically configure both devices for maximum performance. When configured for auto-negotiation, the CS8952 will detect and auto- matically operate full-duplex at 100 Mb/s if the de- vice on the other end of the link segment also supports full-duplex, 100 Mb/s operation, and auto-negotiation ...
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... CS8952 changes between 10 Mb/s and 100 Full 100 Mb/s modes. After a reset, the CS8952 latches the signals on var- ious input pins in order to initialize key registers and goes through a self configuration. This in- cludes calibrating on-chip analog circuitry. Time required for the reset calibration is typically 40 ms. ...
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... The presence of recovered data on the RXD[3:0] bus is indicated by the assertion of RX_DV. RX_DV will remain asserted from the beginning of the preamble (or Start of Frame Delimiter if pream- ble is not used) to the End of Frame Delimiter. Once RX_DV is asserted, valid data will be driven CS8952 End of Frame Delimiter MSB Second ...
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... Transmit errors should be signaled by the MAC by asserting TX_ER for one or more TX_CLK cycles. TX_ER must be synchronous with TX_CLK. This will cause the CS8952 to replace the nibble with a HALT symbol in the frame being transmitted. This invalid data will be detected by the receiving PHY and flagged as a bad frame ...
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... At the beginning of each transaction, the MAC will typically send a sequence of 32 contiguous logic ONE bits on MDIO with 32 corresponding clock cycles on MDC to provide the CS8952 with a pat- tern that it can use to establish synchronization. Optionally, the CS8952 may be configured to oper- ate without the preamble through bit 9 of the PCS Sub-Layer Configuration Register (address 17h) ...
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... The data field is always 16 bits in length, with the most significant bit sent first. 5. CONFIGURATION The CS8952 can be configured in a variety of ways. All control and status information can be accessed via the MII Serial Management Interface. Addi- tionally, many configuration options can be set at power-up or reset times via individual control lines ...
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... CS8952 REGISTERS The CS8952 register set is comprised of the 16-bit status and control registers described below. A de- tailed description each register follows. Register Address 0h Basic Mode Control Register 1h Basic Mode Status Register 2h PHY Identifier #1 3h PHY Identifier #2 4h Auto-Negotiation Advertisement Register 5h Auto-Negotiation Link Partner Ability Register ...
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... Clearing this reset to 0 bit disables auto-negotiation. When this bit is set, the CS8952 enters a low power consumption state. Clearing this bit allows normal operation. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set ...
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... When set, the COL pin will be asserted within 10 bit times in response to the assertion of TX_EN. Upon the deassertion of TX_EN, COL will be deasserted within 4 bit times. When Collision Test is clear, COL functions normally. CS8952 DESCRIPTION 32 ...
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... Full-Duplex operation. This bit reflects the status of the 10BASE-T/Full Duplex bit in the Auto-Negotiation Advertisement Register (address 04h). When this bit is set, it indicates that the CS8952 is capable of 10BASE-T Half-Duplex operation. This bit reflects the status of the 10BASE-T/Half Duplex bit in the Auto-Negotiation Advertisement Register (address 04h) ...
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... CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 RESET DESCRIPTION This bit indicates that the CS8952 has auto-negotia- tion capability. Therefore this bit will always read back a value of 1. When set, this bit indicates that a valid link has been established. Upon a link failure, this bit is cleared and latched ...
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... This register contains bits [3:18] of the OUI. Bit 3 of the OUI is located in bit 15 of the PHY Identifier, bit 4 of the OUI is in bit 14, and so on. Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. CS8952 ...
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... National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. These bits indicate the CS8952 part number. It has been set to a value of 100000. Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set ...
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... This bit may be used to indicate a fault condition to the link partner. Setting this bit will signal to the link partner that a fault condition has occurred. This field determines the advertised capabilities of the CS8952 as shown below. When the bit is set, the corresponding technology will be advertised during auto-negotiation. BIT Capability ...
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... When set, this bit indicates that the link partner is capable of participating in the Next Page exchange. When set, this bit indicates that the link partner has received consistent data from the CS8952. This bit indicates that a fault condition occurred on the far end. When this bit is set and auto-negotiation is enabled, the Remote Fault bit in the Basic Mode Status Register (address 01h) will also be set ...
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... When set, this bit indicates that the link partner is capable of Next Page exchange. This bit is a status bit which indicates to the Manage- ment Layer that the CS8952 supports Next Page capability. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set ...
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... Configuration Register (address 1Ch) is set. When set, this bit indicates to the link partner that the CS8952 can comply with the last received message. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set ...
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... Configuration Register (address 1Ch) is set. When set, an interrupt will be generated each time the CS8952 detects a change in the link status. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set ...
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... Configuration Register (address 1Ch) is set. When set, an interrupt will be generated when a Jab- ber condition is detected by the 10BASE-T MAU. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. CS8952 42 ...
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... Configuration Register (address 1Ch) is set. When set, an interrupt is generated each time a page is received during auto-negotiation. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. CS8952 43 ...
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... FCCR may be read before saturat- ing. This bit is set when the MSB of the Receive Error Count Register (address 15h) becomes set. This should provide ample warning to the management layer so that the RECR may be read before rolling over. CS8952 Remote FCCR RECR ...
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... This bit is self-clearing. This bit is the same as in the Auto-Negotiation Expansion Register (address 06h) When set, this bit indicates that a parallel detection has occurred for a technology that is not currently advertised by the local device. CS8952 45 ...
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... The first page of data will consist of the Base Page, and all successive pages will consist of Next Page data. This bit is self-clearing. This bit is the same as in the Auto-Negotiation Expansion Register (address 06h). CS8952 46 ...
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... Disconnect Counter Read/Write 0000h CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 Disconnect Counter Disconnect Counter RESET This field contains a count of the number of times the CS8952 has lost a Link OK condition. This counter is cleared upon readout and will roll-over to 0000h. CS8952 DESCRIPTION 47 ...
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... False Carrier Counter RESET This field contains a count of the number of times the CS8952 has detected a false-carrier -- that is, the reception of a poorly formed Start-of-Stream Delim- iter (SSD). The counter is incremented at the end of such events to prevent multiple increments. This counter is cleared upon readout and will saturate at FFFFh ...
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... This is valuable for testing purposes to allow a deter- 19h). ministic response to test stimulus without a synchro- nization delay. Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. CS8952 Scrambler Initialization Key ...
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... CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 Receive Error Counter Receive Error Counter RESET This counter increments for each packet in which one or more receive errors is detected that is not due to a collision event. This counter is cleared upon readout and will roll-over to 0000h. CS8952 DESCRIPTION 50 ...
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... This is valuable for testing purposes to allow a deter- 19h). ministic response to test stimulus without a synchro- nization delay. Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. CS8952 Descrambler Initialization Key ...
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... When set, this bit unlocks certain read only control registers for factory testing. Leave clear for proper operation. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. CS8952 Preamble Unlock Regs Fast Test Enable ...
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... If Tx Disable is set while a packet is being transmit- ted, transmission is completed and no subsequent packets are transmitted until Tx Disable is cleared again. Also Disable is cleared while TX_EN is high, the transmitter will remain disabled until TX_EN is deasserted. This prevents fragments from being transmitted onto the network. CS8952 DESCRIPTION 53 ...
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... When set, this bit will reset all digital logic and regis- ters to their initial values. The analog circuitry will not be affected. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. CS8952 54 ...
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... If the 4B5B encoders are being bypassed, this event will be reported by setting RX_DV=0 and RXD[4:0]=11110. If symbol alignment is bypassed, the CS8952 does not detect carrier, and thus will not report bad SSD events. When set, this bit causes the receive 5B4B decoder on the BP4B5B and the transmit 4B5B encoder to be bypassed ...
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... NRZI receive port on the descrambler. The loopback includes all of the 100BASE-TX functionality except for the MLT-3 encoding/decoding and the analog line-interface blocks. When clear, the CS8952 is configured for normal operation. Note: Setting Remote Loopback and PMD Loopback simultaneously will cause neither loopback mode to be entered, and should not be done ...
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... RXD[3:0] as selected by the Code Error Report Select bit and also causes the assertion of TX_ER to transmit a HALT code group. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. CS8952 57 ...
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... This bit may be used to determine the current status of the link. When high, this bit indicates that the CS8952 low power state. This bit is high whenever the CS8952 is receiving valid data direct copy of the state of the RX_DV pin accessible by software ...
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... These bits define the PHY PHYAD[4:0] pins. address used by the management layer to address the PHY. The external logic must know this address in order to select this particular CS8952’s registers individually via the MDIO and MDC pins. CS8952 DESCRIPTION ...
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... Polarity Disable bit. When set, this bit selects 10BASE-T serial mode. on the 10BT_SER When low, this bit selects 10BASE-T nibble mode. pin. This bit will only affect the CS8952 if it has been con- figured for 10 Mb/s operation. CS8952 ...
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... When clear, link pulses are disabled and a good link condition is forced. If link pulses are disabled during 100 Mb/s operation with auto-negotiation enabled, the CS8952 will go into 10 Mb/s mode. If operating in 100 Mb/s mode with no auto-negotiation, then clear- ing this bit has no effect. ...
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... CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 RESET When set, the jabber function is enabled. When clear, and if the CS8952 is in 10BASE-T full-duplex or 10BASE-T ENDEC loopback mode, the jabber function is disabled. Note: When the National Compatibility Mode bit (bit 7) is set, the Jabber function may also be disabled for 10BASE-T half-duplex, although this is not rec- ommended ...
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... RES con- nection. 7.4 Clocking Schemes The CS8952 may be clocked using one of three possible schemes: using a 25 MHz crystal and the internal oscillator, using an external oscillator sup- CS8952 HFBR-5103 FIBER TRANS ...
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... Transformer Fiber Interface Table 7. Support Component Manufactures Each CS8952 power pin should be connected to a 0.1 µF bypass capacitor and then to the power plane. The bypass capacitors should be located as close to its corresponding power pin as possible. Connect ground pins directly to the ground plane. ...
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... RJ45 and the primary (chip) side facing the analog side (pins 76-100) of CS8952. Place the CS8952 in turn as close possible. • Use the bottom layer for signal routing as a sec- ond choice. You may place all components on the top layer ...
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... Table 8. RJ-45 Wiring transceiver, and the RX_NRZ+/- and SIG- NAL+/- termination components must be kept close to the CS8952. • Locate the crystal as close to the CS8952 as possible, running short traces on the component side in order to reduce parasitic load capaci- tance. • Add bulk capacitance at each connector where power may be supplied ...
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... VDD 11 VSS 12 VSS 13 RX_EN 14 RESET 15 REPEATER 16 CLK25 17 VSS 18 VDD 19 VSS 20 VDD_MII 21 VSS 22 10BT_SER 23 TEST0 24 TEST1 25 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 CS8952 100-pin TQFP ( mm) CS8952 75 RSVD 74 RSVD 73 LED5 72 LED4 71 LED3 70 LED2 69 LED1 68 SPD10 67 SPD100 66 VDD_MII 65 VSS 64 PWRDN 63 ISODEF 62 BPSCR 61 TXSLEW1 ...
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... RX_CLK and TX_CLK. MDIO - Management Data Input/Output. Bi-Directional, Pin 27. Bi-directional signal used to transfer management data between the CS8952 and the Ethernet controller. In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin should be pulled high during power-up or reset, and the MDIO pin should have an external 1.5 kΩ pull-up resistor. For systems not required to drive external connectors and cables as described in the IEEE802 ...
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... RX_EN allows the received data signals of multiple PHY transceivers to share the same MII bus. This pin includes a weak internal pull-up (> 150 kΩ), or the value may be set by an external 10 kΩ pull pull-down resistor. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 CS8952 69 ...
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... TX_CLK - Transmit Clock. Input/Tri-State Output, Pin 42. Continuous clock signal used by the CS8952 as a reference clock to sample TXD[3:0], TX_ER, and TX_EN. TX_CLK can be referenced either internally (Output Mode) or externally (Input Mode) based upon the value of the TCM pin at power- reset. ...
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... TX_EN must be pulled up to VDD_MII. TX_ER/TXD4 - Transmit Error Encoding/Transmit Data 4. Input, Pin 38. When high, TX_ER indicates to the CS8952 that a transmit error has occurred. If TX_ER is asserted simultaneously with TX_EN in 100 Mb/s mode, the CS8952 will ignore the data on the TXD[3:0] pins and transmit one or more 100 Mb/s HALT symbols in its place Mb/s mode, TX_ER has no effect on the transmitted data ...
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... CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 Speed Forced/Auto 10 Mb/s Forced 100 Mb/s Forced 100 Mb/s Forced 100/10 Mb/s Auto-Neg 10 Mb/s Auto-Neg 10 Mb/s Auto-Neg 100 Mb/s Auto-Neg 100 Mb/s Auto-Neg CS8952 Full/Half Duplex Full Half Full Full/Half Half Full Half Full 72 ...
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... At power- reset, the value on this pin is latched into bit 13 of the Loopback, Bypass and Receiver Error Mask Register (address 18h). This pin includes a weak internal pull-down (> 20 kΩ), or the value may be set by an external 4.7 kΩ pull-up or pull-down resistor. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 CS8952 73 ...
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... This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin. LPBK - Loopback Enable. Input, Pin 51. When this pin is asserted high and the CS8952 is operating in 100 Mb/s mode, the CS8952 will perform a local loopback inside the PMD block, routing the scrambled NRZI output to the NRZI input port on the descrambler ...
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... When this active-low input is asserted during power-up or reset, the CS8952 will exit reset in a low power configuration, where the only circuitry enabled is that necessary to maintain the media impedance. The CS8952 will remain in a low power state until RESET pin is asserted or the MDC pin toggles. ...
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... SPD10 - 10 Mb/s Speed Indication. Output, Pin 68. This pin is asserted high when the CS8952 is configured for 10 Mb/s operation. This pin can be used to drive a low-current LED to indicate 10 Mb/s operation. SPD100 - 100 Mb/s Speed Indication. Output, Pin 67. ...
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... General Pins CLK25 - 25 MHz Clock. Output, Pin 17 MHz Clock is output on this pin when the CS8952 is configured to use an external reference transmit clock in TX_CLK IN MASTER mode. See the pin description for the Transmit Clock Mode Initialization pin (TCM) for more information on TX_CLK operating modes. ...
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... RESET - Reset. Input, Pin 15. This active high input initializes the CS8952, and causes the CS8952 to latch the input signal on the following pins: COL/PHYAD0, CRS/PHYAD2, RX_ER/PHYAD4/RXD4, 10BT_SER, BP4B5B, BPALIGN, BPSCR, ISODEF, REPEATER, RXD[1]/PHYAD1, and RXD[3]/PHYAD3. XTAL_I - Crystal Input, Pin 96. ...
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... CS8952 A A1 MILLIMETERS MIN MAX --- 1.60 0.15 0.27 16.30 14.10 16.30 14.10 0.60 0.75 7.00° 79 ...
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... ORDERING INFORMATION Part # CS8952-CQZ CS8952-IQZ 11. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS8952-CQZ CS8952-IQZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 Temperature Range 0 °C to +70 °C -40 °C to +85 °C Peak Reflow Temp MSL Rating* 260 ° ...
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... Cirrus Logic, Cirrus, CrystalLAN, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DS206F1 Changes Initial Release. Added industrial temp range device. Added MSL data. CS8952 81 ...