DS90CR216MTD/NOPB National Semiconductor, DS90CR216MTD/NOPB Datasheet

IC RCVR 21BIT CHAN LINK 48TSSOP

DS90CR216MTD/NOPB

Manufacturer Part Number
DS90CR216MTD/NOPB
Description
IC RCVR 21BIT CHAN LINK 48TSSOP
Manufacturer
National Semiconductor
Type
Receiverr
Datasheet

Specifications of DS90CR216MTD/NOPB

Protocol
RS644
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Other names
*DS90CR216MTD
*DS90CR216MTD/NOPB
DS90CR216MTD

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS90CR216MTD/NOPB
Manufacturer:
STM
Quantity:
9 000
© 2009 National Semiconductor Corporation
+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link -
66 MHz
General Description
The DS90CR215 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in par-
allel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CR216 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL data. At
a transmit clock frequency of 66 MHz, 21 bits of TTL data are
transmitted at a rate of 462 Mbps per LVDS data channel.
Using a 66 MHz clock, the data throughput is 1.386 Gbit/s
(173 Mbytes/s).
The multiplexing of the data lines provides a substantial cable
reduction. Long distance parallel single-ended buses typically
require a ground wire per active signal (and have very limited
noise rejection capability). Thus, for a 21-bit wide data and
one clock, up to 44 conductors are required. With the Channel
Link chipset as few as 9 conductors (3 data pairs, 1 clock pair
and a minimum of one ground) are needed. This provides a
80% reduction in required cable width, which provides a sys-
tem cost savings, reduces connector physical size and cost,
and reduces shielding requirements due to the cables' smaller
form factor.
Block Diagrams
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
See NS Package Number MTD48
Order Number DS90CR215MTD
DS90CR215
DS90CR215/DS90CR216
12909
1290901
The 21 CMOS/TTL inputs can support a variety of signal
combinations. For example, five 4-bit nibbles plus 1 control,
or two 9-bit (byte + parity) and 3 control.
Features
See DS90CR216AMTD with Improved AC Specifications
Single +3.3V supply
Chipset (Tx + Rx) power consumption <250 mW (typ)
Power-down mode (<0.5 mW total)
Up to 173 Megabytes/sec bandwidth
Up to 1.386 Gbps data throughput
Narrow bus reduces cable size
290 mV swing LVDS devices for low EMI
+1V common mode range (around +1.2V)
PLL requires no external components
Low profile 48-lead TSSOP package
Rising edge data strobe
Compatible with TIA/EIA-644 LVDS standard
ESD Rating > 7 kV
Operating Temperature: −40°C to +85°C
Recommended Alternative Device
See NS Package Number MTD48
Order Number DS90CR216MTD
DS90CR216
www.national.com
June 5, 2009
1290927

Related parts for DS90CR216MTD/NOPB

DS90CR216MTD/NOPB Summary of contents

Page 1

... Block Diagrams DS90CR215 Order Number DS90CR215MTD See NS Package Number MTD48 TRI-STATE® registered trademark of National Semiconductor Corporation. © 2009 National Semiconductor Corporation DS90CR215/DS90CR216 The 21 CMOS/TTL inputs can support a variety of signal combinations. For example, five 4-bit nibbles plus 1 control, or two 9-bit (byte + parity) and 3 control. ...

Page 2

Connection Diagrams DS90CR215 Typical Application www.national.com 1290921 2 1290922 DS90CR216 1290923 ...

Page 3

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Receiver Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Duration ...

Page 4

Symbol Parameter I Transmitter Supply Current Worst Case (with CCTW Loads) I Transmitter Supply Current Power Down CCTZ RECEIVER SUPPLY CURRENT I Receiver Supply Current Worst Case CCRW I Receiver Supply Current Power Down CCRZ Note 1: “Absolute Maximum Ratings” ...

Page 5

Symbol Parameter TPPos5 Transmitter Output Pulse Position for Bit5 TPPos6 Transmitter Output Pulse Position for Bit6 TCIP TxCLK IN Period (Figure 6) TCIH TxCLK IN High Time (Figure 6) TCIL TxCLK IN Low Time (Figure 6) TSTC TxIN Setup to ...

Page 6

AC Timing Diagrams FIGURE 2. DS90CR215 (Transmitter) LVDS Output Load and Transition Times FIGURE 3. DS90CR216 (Receiver) CMOS/TTL Output Load and Transition Times FIGURE 4. D590CR215 (Transmitter) Input Clock Transition Time www.national.com FIGURE 1. “Worst Case” Test Pattern 1290903 1290905 ...

Page 7

Note 8: Measurements DIFF Note 9: TCCS measured between earliest and latest LVDS edges → Note 10: TxCLK Differential Low High Edge FIGURE 5. D590CR215 (Transmitter) Channel-to-Channel Skew FIGURE 6. D590CR215 (Transmitter) Setup/Hold and High/Low Times ...

Page 8

FIGURE 8. DS90CR215 (Transmitter) Clock In to Clock Out Delay FIGURE 9. D590CR216 (Receiver) Clock In to Clock Out Delay FIGURE 10. DS90CR215 (Transmitter) Phase Lock Loop Set Time www.national.com 1290929 1290912 8 1290913 ...

Page 9

FIGURE 11. DS9OCR216 (Receiver) Phase Lock Loop Set Time FIGURE 12. Seven Bits of LVDS in Once Clock Cycle FIGURE 13. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CR215) 1290914 9 1290915 1290916 www.national.com ...

Page 10

FIGURE 16. Transmitter LVDS Output Pulse Position Measurement www.national.com FIGURE 14. Transmitter Powerdown Delay FIGURE 15. Receiver Powerdown Delay 10 1290917 1290918 1290919 ...

Page 11

FIGURE 17. Receiver LVDS Input Strobe Position 11 1290928 www.national.com ...

Page 12

C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos—Transmitter output pulse position (min and max) ≥ RSKM Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note Cycle-to-cycle ...

Page 13

Pin Name I/O No Power supply pins for TTL outputs. CC GND I 5 Ground pins for TTL outputs. PLL Power supply for PLL. CC PLL GND 1 2 Ground pin for PLL. LVDS ...

Page 14

DECOUPLING CAPACITORS Bypassing capacitors are needed to reduce the impact of switching noise which could limit performance. For a conser- vative approach three parallel-connected decoupling capaci- tors (Multi-Layered Ceramic type in surface mount form factor) between each V and the ...

Page 15

FIGURE 21. Single-Ended and Differential Waveforms 15 1290926 www.national.com ...

Page 16

Physical Dimensions www.national.com inches (millimeters) unless otherwise noted Order Number DS90CR215MTD or DS90CR216MTD NS Package Number MTD48 16 ...

Page 17

Notes 17 www.national.com ...

Page 18

... For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...

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