DS90CR287MTD/NOPB National Semiconductor, DS90CR287MTD/NOPB Datasheet

IC TX 28BIT CHAN LINK 56TSSOP

DS90CR287MTD/NOPB

Manufacturer Part Number
DS90CR287MTD/NOPB
Description
IC TX 28BIT CHAN LINK 56TSSOP
Manufacturer
National Semiconductor
Type
Driverr
Datasheet

Specifications of DS90CR287MTD/NOPB

Number Of Drivers/receivers
3/0
Protocol
RS644
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
56-TSSOP
Supply Current
60mA
Supply Voltage Range
3V To 3.6V
Driver Case Style
TSSOP
No. Of Pins
56
Operating Temperature Range
-10°C To +70°C
Msl
MSL 2 - 1 Year
Device Type
Line
Filter Terminals
SMD
Rohs Compliant
Yes
Esd Hbm
7kV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
*DS90CR287MTD
*DS90CR287MTD/NOPB
DS90CR287MTD

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Part Number
Manufacturer
Quantity
Price
Part Number:
DS90CR287MTD/NOPB
Manufacturer:
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Quantity:
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© 2004 National Semiconductor Corporation
DS90CR287/DS90CR288A
+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel
Link-85 MHz
General Description
The DS90CR287 transmitter converts 28 bits of LVCMOS/
LVTTL data into four LVDS (Low Voltage Differential Signal-
ing) data streams. A phase-locked transmit clock is transmit-
ted in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bits of input data are
sampled and transmitted. The DS90CR288A receiver con-
verts the four LVDS data streams back into 28 bits of
LVCMOS/LVTTL data. At a transmit clock frequency of 85
MHz, 28 bits of TTL data are transmitted at a rate of 595
Mbps per LVDS data channel. Using a 85 MHz clock, the
data throughput is 2.38 Gbit/s (297.5 Mbytes/sec).
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high-speed TTL interfaces.
Block Diagrams
See NS Package Number MTD56
Order Number DS90CR287MTD
DS90CR287
DS101087
10108701
Features
n 20 to 85 MHz shift clock support
n 50% duty cycle on receiver output clock
n 2.5 / 0 ns Set & Hold Times on TxINPUTs
n Low power consumption
n
n Narrow bus reduces cable size and cost
n Up to 2.38 Gbps throughput
n Up to 297.5 Mbytes/sec bandwidth
n 345 mV (typ) swing LVDS devices for low EMI
n PLL requires no external components
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 56-lead TSSOP package
±
1V common-mode range (around +1.2V)
Order Number DS90CR288AMTD
See NS Package Number MTD56
DS90CR288A
www.national.com
July 2004
10108727

Related parts for DS90CR287MTD/NOPB

DS90CR287MTD/NOPB Summary of contents

Page 1

... TTL interfaces. Block Diagrams DS90CR287 Order Number DS90CR287MTD See NS Package Number MTD56 © 2004 National Semiconductor Corporation Features MHz shift clock support n 50% duty cycle on receiver output clock n 2 Set & Hold Times on TxINPUTs n Low power consumption ± ...

Page 2

Pin Diagram for TSSOP Packages DS90CR287 Typical Application www.national.com 10108721 2 DS90CR288A 10108722 10108723 ...

Page 3

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage −0. CMOS/TTL Output Voltage −0. LVDS Receiver Input Voltage −0. LVDS Driver Output Voltage −0. LVDS Output Short Circuit ...

Page 4

Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter TRANSMITTER SUPPLY CURRENT I Transmitter Supply Current Worst CCTW Case (with Loads) I Transmitter Supply Current Power CCTZ Down RECEIVER SUPPLY CURRENT I Receiver Supply Current ...

Page 5

Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol CLHT CMOS/TTL Low-to-High Transition Time (Figure 3) CHLT CMOS/TTL High-to-Low Transition Time (Figure 3) RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 15) RSPos1 Receiver ...

Page 6

AC Timing Diagrams FIGURE 2. DS90CR287 (Transmitter) LVDS Output Load and Transition Times FIGURE 3. DS90CR288A (Receiver) CMOS/TTL Output Load and Transition Times FIGURE 4. DS90CR287 (Transmitter) Input Clock Transition Time FIGURE 5. DS90CR287 (Transmitter) Setup/Hold and High/Low Times www.national.com ...

Page 7

AC Timing Diagrams (Continued) FIGURE 6. DS90CR288A (Receiver) Setup/Hold and High/Low Times FIGURE 7. DS90CR287 (Transmitter) Clock In to Clock Out Delay FIGURE 8. DS90CR288A (Receiver) Clock In to Clock Out Delay FIGURE 9. DS90CR287 (Transmitter) Phase Lock Loop Set ...

Page 8

AC Timing Diagrams FIGURE 10. DS90CR288A (Receiver) Phase Lock Loop Set Time FIGURE 11. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs www.national.com (Continued) FIGURE 12. Transmitter Powerdown Delay 8 10108714 10108716 10108717 ...

Page 9

AC Timing Diagrams (Continued) FIGURE 14. Transmitter LVDS Output Pulse Position Measurement FIGURE 13. Receiver Powerdown Delay 9 10108718 10108719 www.national.com ...

Page 10

AC Timing Diagrams www.national.com (Continued) FIGURE 15. Receiver LVDS Input Strobe Position 10 10108728 ...

Page 11

AC Timing Diagrams C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos — Transmitter output pulse position (min and max) RSKM ≥ Cable Skew (type, length) + Source ...

Page 12

DS90CR288A MTD56 (TSSOP) Package Pin Description — Channel Link Receiver (Continued) Pin Name I/O No. GND I 5 Ground pins for TTL outputs. PLL Power supply for PLL. CC PLL GND I 2 Ground pin for PLL. ...

Page 13

Applications Information The TSSOP version of the DS90CR287 and DS90CR288A are backward compatible with the existing 5V Channel Link transmitter/receiver pair (DS90CR283, DS90CR284). To up- grade from 3.3V system the following must be addressed: 1. Change ...

Page 14

Applications Information ramic type in surface mount form factor) between each V and the ground plane(s) are recommended. The three ca- pacitor values are 0.1 µF, 0.01 µF and 0.001 µF. An example is shown in Figure 18. The designer ...

Page 15

Applications Information Input Clock section. Do not power up and enable (PWR DOWN = HIGH) the transmitter without a valid clock signal applied to the TxCLK IN pin. The CHANNEL LINK chipset is designed to protect itself from accidental loss ...

Page 16

... BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. ...

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