PIC16F688-I/P

Manufacturer Part NumberPIC16F688-I/P
Description14 PIN, 7 KB FLASH, 256 RAM, 12 I/O
ManufacturerMicrochip Technology Inc.
PIC16F688-I/P datasheet
 


Specifications of PIC16F688-I/P

A/d Inputs8-Channel, 10-BitComparators2
Cpu Speed5 MIPSEeprom Memory256 Bytes
Input Output12InterfaceUSART
Memory TypeFlashNumber Of Bits8
Package Type14-pin PDIPProgrammable Memory7K Bytes
Ram Size256 BytesSpeed20 MHz
Timers1-8-bit, 1-16-bitVoltage, Range2-5.5 V
Lead Free Status / Rohs StatusRoHS Compliant part Electrostatic Device  
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PIC16F688
Data Sheet
14-Pin Flash-Based, 8-Bit
CMOS Microcontrollers with
nanoWatt Technology
© 2006 Microchip Technology Inc.
DS41203C

PIC16F688-I/P Summary of contents

  • Page 1

    ... Microchip Technology Inc. PIC16F688 Data Sheet 14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology DS41203C ...

  • Page 2

    ... Company’s quality system processes and procedures are for its PICmicro ® 8-bit MCUs, K EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. L ® code hopping devices, Serial EE OQ © 2006 Microchip Technology Inc. ...

  • Page 3

    ... Flash/Data EEPROM retention: > 40 years Program Memory Device Flash (words) PIC16F688 4096 © 2006 Microchip Technology Inc. PIC16F688 Low-Power Features: • Standby Current 2.0V, typical • Operating Current kHz, 2.0V, typical - 220 MHz, 2.0V, typical • Watchdog Timer Current 2.0V, typical Peripheral Features: • ...

  • Page 4

    ... PIC16F688 Pin Diagram (PDIP, SOIC, TSSOP) 14-pin PDIP, SOIC, TSSOP RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/V RC5/RX/DT RC4/C2OUT/TX/CK RC3/AN7 TABLE 1: PIC16F688 14-PIN SUMMARY (PDIP, SOIC, TSSOP) I/O Pin Analog Comparators RA0 13 AN0/ULPWU C1IN+ RA1 12 AN1 C1IN- RA2 11 AN2 C1OUT RA3 4 — RA4 3 AN3 RA5 2 — ...

  • Page 5

    ... Pin Diagram (QFN) 16-pin QFN RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/V RC5/RX/DT TABLE 2: PIC16F688 16-PIN SUMMARY (QFN) I/O Pin Analog Comparators RA0 12 AN0/ULPWU C1IN+ RA1 11 AN1 C1IN- RA2 10 AN2 C1OUT RA3 3 — RA4 2 AN3 RA5 1 — RC0 9 AN4 C2IN+ RC1 8 AN5 C2IN- RC2 7 AN6 ...

  • Page 6

    ... PIC16F688 Table of Contents 1.0 Device Overview ......................................................................................................................................................................... 5 2.0 Memory Organization .................................................................................................................................................................. 7 3.0 Clock Sources ........................................................................................................................................................................... 21 4.0 I/O Ports .................................................................................................................................................................................... 33 5.0 Timer0 Module .......................................................................................................................................................................... 45 6.0 Timer1 Module with Gate Control.............................................................................................................................................. 49 7.0 Comparator Module................................................................................................................................................................... 55 8.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 65 9.0 Data EEPROM and Flash Program Memory Control ................................................................................................................ 77 10.0 Enhanced Universal Asynchronous Receiver Transmitter (EUSART) ...................................................................................... 83 11 ...

  • Page 7

    ... DEVICE OVERVIEW The PIC16F688 is covered by this data sheet available in 14-pin PDIP, SOIC, TSSOP and QFN packages. Figure 1-1 shows a block diagram of the PIC16F688 device. Table 1-1 shows the pinout description. FIGURE 1-1: PIC16F688 BLOCK DIAGRAM Configuration Flash Program Memory Program ...

  • Page 8

    ... PIC16F688 TABLE 1-1: PIC16F688 PINOUT DESCRIPTION Name Function RA0/AN0/C1IN+/ICSPDAT/ULPWU RA0 AN0 C1IN+ ICSPDAT ULPWU RA1/AN1/C1IN-/V /ICSPCLK RA1 REF AN1 C1IN- V ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RA2 AN2 T0CKI INT C1OUT RA3/MCLR/V RA3 PP MCLR V RA4/AN3/T1G/OSC2/CLKOUT RA4 AN3 T1G OSC2 CLKOUT RA5/T1CKI/OSC1/CLKIN RA5 T1CKI OSC1 ...

  • Page 9

    ... Program Memory Organization The PIC16F688 has a 13-bit program counter capable of addressing program memory space. Only the first (0000h-01FFF) for the PIC16F688 is physically implemented. Accessing a location above these boundaries will cause a wraparound within the first space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1) ...

  • Page 10

    ... PIC16F688 FIGURE 2-2: PIC16F688 SPECIAL FUNCTION REGISTERS File Address (1) Indirect addr. 00h Indirect addr. TMR0 01h OPTION_REG 81h PCL 02h PCL STATUS 03h STATUS FSR 04h FSR PORTA 05h TRISA 06h PORTC 07h TRISC 08h 09h PCLATH 0Ah PCLATH INTCON 0Bh ...

  • Page 11

    ... TABLE 2-1: PIC16F688 SPECIAL REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 01h TMR0 Timer0 Module’s register 02h PCL Program Counter’s (PC) Least Significant Byte 03h ...

  • Page 12

    ... PIC16F688 TABLE 2-2: PIC16F688 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG RAPU INTEDG 82h PCL Program Counter’s (PC) Least Significant Byte 83h ...

  • Page 13

    ... TABLE 2-3: PIC16F688 SPECIAL REGISTERS SUMMARY BANK 2 Addr Name Bit 7 Bit 6 Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 101h TMR0 Timer0 Module’s register 102h PCL Program Counter’s (PC) Least Significant Byte 103h ...

  • Page 14

    ... PIC16F688 TABLE 2-4: PIC16F688 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3 Addr Name Bit 7 Bit 6 Bank 3 180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 181h OPTION_REG RAPU INTEDG 182h PCL Program Counter’s (PC) Least Significant Byte 183h ...

  • Page 15

    ... Status bits. For other instructions not affect- ing any Status bits (see Section 12.0 “Instruction Set Summary”). Note 1: Bits IRP and RP1 of the STATUS register are not used by the PIC16F688 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products ...

  • Page 16

    ... PIC16F688 2.2.2.2 OPTION Register The OPTION register is a readable and writable register, which contains various control bits to configure: • Timer0/WDT prescaler • External RA2/INT interrupt • Timer0 • Weak pull-ups on PORTA REGISTER 2-2: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 RAPU INTEDG ...

  • Page 17

    ... GIE of the INTCON register. User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. R/W-0 R/W-0 R/W-0 INTE RAIE T0IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) PIC16F688 R/W-0 R/W-x INTF RAIF bit Bit is unknown DS41203C-page 15 ...

  • Page 18

    ... PIC16F688 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 EEIE ADIE RCIE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ...

  • Page 19

    ... GIE bit of the INTCON register. User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. R/W-0 R/W-0 R/W-0 C2IF C1IF OSFIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared PIC16F688 R-0 R/W-0 TXIF TMR1IF bit Bit is unknown DS41203C-page 17 ...

  • Page 20

    ... PIC16F688 2.2.2.6 PCON Register The Power Control (PCON) register (see Register 2-6) contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOR ...

  • Page 21

    ... Microchip Technology Inc. 2.3.2 STACK The PIC16F688 family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch ...

  • Page 22

    ... Writing to the INDF register indirectly results operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit of the STATUS register, as shown in Figure 2-4. FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC16F688 Direct Addressing From Opcode RP1 RP0 6 ...

  • Page 23

    ... MHz 111 INTOSC 4 MHz 110 2 MHz 101 1 MHz 100 500 kHz 011 250 kHz 010 125 kHz 001 31 kHz 000 Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM) PIC16F688 /4 output OSC FOSC<2:0> SCS<0> System Clock (CPU and Peripherals) DS41203C-page 21 ...

  • Page 24

    ... PIC16F688 3.2 Oscillator Control The Oscillator Control (OSCCON) register (Figure 3-1) controls the system clock and frequency selection options. The OSCCON register contains the following bits: • Frequency selection bits (IRCF) • Frequency Status bits (HTS, LTS) • System clock control bits (OSTS, SCS) ...

  • Page 25

    ... MHz 125 kHz to 8 MHz FIGURE 3-2: Clock from Ext. System Note 1: Alternate pin functions are listed in Section 1.0 “Device Overview”. MCU design is PIC16F688 Oscillator Delay Oscillator Warm-Up Delay (T ) WARM 2 instruction cycles 1 cycle of each 1024 Clock Cycles (OST (approx.) ...

  • Page 26

    ... PIC16F688 3.4.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 3-3). The mode selects a low, medium or high gain setting of the internal inverter- amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier ...

  • Page 27

    ... System Clock Source (SCS) bit of the OSCCON register to ‘1’ or enable Two-Speed Start-up by setting the IESO bit in the Configuration Word register (CONFIG) to ‘1’. The HF Internal Oscillator (HTS) bit of the OSCCON register indicates whether the HFINTOSC is stable or not. PIC16F688 (High-Frequency Internal (Low-Frequency Internal See Section 11.0 “ ...

  • Page 28

    ... PIC16F688 3.5.2.1 OSCTUNE Register The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 3-2). The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. REGISTER 3-2: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 ...

  • Page 29

    ... OSCCON register are set to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency. © 2006 Microchip Technology Inc. PIC16F688 3.5.5 HF AND LF INTOSC CLOCK SWITCH TIMING When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power (see Figure 3-6) ...

  • Page 30

    ... PIC16F688 FIGURE 3-6: INTERNAL OSCILLATOR SWITCH TIMING ( HFINTOSC LFINTOSC (FSCM and WDT disabled) HFINTOSC LFINTOSC IRCF <2:0> 0 System Clock Note 1: When going from LF to HF. HFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC LFINTOSC IRCF <2:0> System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time 2-cycle Sync HFINTOSC IRCF < ...

  • Page 31

    ... OSTS bit of the OSCCON register to remain clear. © 2006 Microchip Technology Inc. PIC16F688 When the Oscillator module is configured for LP modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.4.1 “Oscillator Start-up Timer (OST)”). The OST will suspend program execution until 1024 oscillations are counted ...

  • Page 32

    ... PIC16F688 3.7.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator. FIGURE 3-7: TWO-SPEED START-UP ...

  • Page 33

    ... Fail-Safe circuit is not active Clock during oscillator start-up (i.e., after exiting Failure Detected Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit of the OSCCON register to verify the oscillator start-up and that the system clock completed. PIC16F688 switchover has successfully DS41203C-page 31 ...

  • Page 34

    ... PIC16F688 FIGURE 3-9: FSCM TIMING DIAGRAM Sample Clock System Clock Output Clock Monitor Output (Q) OSCFIF Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES ...

  • Page 35

    ... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R-1 R/W-1 TRISA4 TRISA3 TRISA2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared PIC16F688 ; ;Init PORTA ;Set RA<2:0> to ;digital I/O ; ;digital I/O ;Set RA<3:2> as inputs ;and set RA<5:4,1:0> ;as outputs R/W-0 ...

  • Page 36

    ... PIC16F688 4.2 Additional Pin Functions Every PORTA pin on the PIC16F688 has an interrupt- on-change option and a weak pull-up option. PORTA also provides an Ultra Low-Power Wake-up option. The next three sections describe these functions. 4.2.1 ANSEL REGISTER The ANSEL register is used to configure the Input mode of an I/O pin to analog ...

  • Page 37

    ... WPUA2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 IOCA4 IOCA3 IOCA2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared PIC16F688 R/W-1 R/W-1 WPUA1 WPUA0 bit Bit is unknown R/W-0 R/W-0 IOCA1 IOCA0 bit Bit is unknown ...

  • Page 38

    ... PIC16F688 4.2.4 ULTRA LOW-POWER WAKE-UP The Ultra Low-Power Wake-up (ULPWU) on RA0 allows a slow falling voltage to generate an interrupt- on-change on RA0 without excess current consump- tion. The mode is selected by setting the ULPWUE bit of the PCON register. This enables a small current sink which can be used to discharge a capacitor on RA0. ...

  • Page 39

    ... A/D • an analog input to the comparator • an analog input to the Ultra Low-Power Wake-up • In-Circuit Serial Programming™ data (1) Analog Input Mode V DD Weak RAPU - + ULP 0 1 (1) Analog Vss Input Mode ULPWUE PORTA PIC16F688 V DD I/O PIN V SS DS41203B-page 37 ...

  • Page 40

    ... PIC16F688 4.2.5.2 RA1/AN1/C1IN-/V /ICSPCLK REF Figure 4-2 shows the diagram for this pin. The RA1 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the A/D • an analog input to the comparator • a voltage reference input for the A/D • ...

  • Page 41

    ... TRISA RD TRISA RD PORTA IOCA RD IOCA Interrupt-on- change To T1G To A/D Converter Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT Enable. 2: With CLKOUT option. 3: Analog Input mode is ANSEL. PIC16F688 BLOCK DIAGRAM OF RA4 (3) Analog Input Mode (1) CLK Modes Weak RAPU Oscillator Circuit OSC1 V DD ...

  • Page 42

    ... PIC16F688 4.2.5.6 RA5/T1CKI/OSC1/CLKIN Figure 4-6 shows the diagram for this pin. The RA5 pin is configurable to function as one of the following: • a general purpose I/O • a Timer1 clock input • a crystal/resonator connection • a clock input DS41203B-page 40 FIGURE 4-6: BLOCK DIAGRAM OF RA5 INTOSC Mode ...

  • Page 43

    ... T0SE PSA PS2 PS1 RA4 RA3 RA2 RA1 TRISA4 TRISA3 TRISA2 TRISA1 WPUA4 — WPUA2 WPUA1 WPUA0 PIC16F688 Value on Value on Bit 0 all other POR, BOR Resets ANS0 1111 1111 1111 1111 CM0 0000 0000 0000 0000 BOR --01 --qq --0u --uu RAIF 0000 000x ...

  • Page 44

    ... PIC16F688 4.3 PORTC PORTC is a general purpose I/O port consisting of 6 bidirectional pins. The pins can be configured for either digital I/O or analog input to A/D converter or compara- tor. For specific information about individual functions such as the EUSART or the A/D converter, refer to the appropriate section in this data sheet ...

  • Page 45

    ... I/O • an analog input for the A/D Converter FIGURE 4-8: Data Bus PORTC I/O Pin Q TRISC TRISC RD PORTC To A/D Converter Note 1: Analog Input mode comes from ANSEL. PIC16F688 BLOCK DIAGRAM OF RC2 AND RC3 V DD I/O Pin V SS Analog Input (1) Mode DS41203B-page 43 ...

  • Page 46

    ... PIC16F688 4.3.5 RC4/C2OUT/TX/CK Figure 4-9 shows the diagram for this pin. The RC4 is configurable to function as one of the following: • a general purpose I/O • a digital output from the comparator • a digital I/O for the EUSART FIGURE 4-9: BLOCK DIAGRAM OF RC4 (1) USART Select ...

  • Page 47

    ... The incrementing edge is determined by the T0SE bit of the OPTION register. Counter mode is selected by setting the T0CS bit of the OPTION register to ‘1’. 8-bit Prescaler PSA 8 PS<2:0> 16-bit 16 PSA WDTPS<3:0> PIC16F688 Data Bus 8 1 Sync TMR0 2 Tcy 0 Set Flag bit T0IF on Overflow 1 WDT ...

  • Page 48

    ... PIC16F688 5.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. ...

  • Page 49

    ... Bit 4 Bit 3 Bit 2 Bit 1 INTE RAIE T0IF INTF T0SE PSA PS2 PS1 PIC16F688 R/W-1 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown Value on Value on Bit 0 all other POR, BOR Resets xxxx xxxx uuuu uuuu RAIF 0000 000x 0000 000x ...

  • Page 50

    ... PIC16F688 6.0 TIMER1 MODULE WITH GATE CONTROL The Timer1 module is a 16-bit timer/counter with the following features: • 16-bit timer/counter register pair (TMR1H:TMR1L) • Programmable internal or external clock source • 3-bit prescaler • Optional LP oscillator • Synchronous or asynchronous operation • Timer1 gate (count enable) via comparator or T1G pin • ...

  • Page 51

    ... The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1. © 2006 Microchip Technology Inc. PIC16F688 6.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks ...

  • Page 52

    ... PIC16F688 6.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • Timer1 interrupt enable bit of the PIE1 register • ...

  • Page 53

    ... TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CM2CON1 register Timer1 gate source. © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T1CKPS0 T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) /4) PIC16F688 R/W-0 R/W-0 TMR1CS TMR1ON bit Bit is unknown DS41203C-page 51 ...

  • Page 54

    ... PIC16F688 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Name Bit 7 Bit 6 Bit 5 CMCON1 — — — INTCON GIE PEIE T0IE PIE1 EEIE ADIE RCIE PIR1 EEIF ADIF RCIF TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TMR1L ...

  • Page 55

    ... Output synchronization to Timer1 clock input • Programmable voltage reference Note: Only Comparator C2 can be linked to Timer1. © 2006 Microchip Technology Inc. PIC16F688 7.1 Comparator Overview A comparator is shown in Figure 7-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at V ...

  • Page 56

    ... PIC16F688 FIGURE 7-2: COMPARATOR C1 OUTPUT BLOCK DIAGRAM C1INV C1 Note 1: Q1 and Q3 are phases of the four-phase system clock ( held high during Sleep mode. FIGURE 7-3: COMPARATOR C2 OUTPUT BLOCK DIAGRAM C2INV C2 Note 1: Comparator output is latched on falling edge of Timer1 clock source and Q3 are phases of the four-phase system clock ( held high during Sleep mode ...

  • Page 57

    ... Pins configured as digital inputs will convert as an analog input, according to the input specification. . The analog SS and the DD 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified 0. LEAKAGE V 0.6V T ±500 nA Vss PIC16F688 IC To ADC Input DS41203C-page 55 ...

  • Page 58

    ... PIC16F688 7.2 Comparator Configuration There are eight modes of operation for the comparator. The CM<2:0> bits of the CMCON0 register are used to select these modes as shown in Figure 7-5. I/O lines change as a function of the mode and are designated as follows: • Analog function (A): digital input buffer is disabled • ...

  • Page 59

    ... CM<2:0> = 110 A C1IN- C1OUT C1 D C1OUT(pin) A C2IN- C2OUT C2 A C2IN+ D C2OUT(pin) CV Module REF Comparators Off (Lowest Power) CM<2:0> = 111 I/O C1IN- C1OUT I/O C1IN+ I/O C2IN- C2OUT I/O C2IN+ CIS = Comparator Input Switch (CMCON0<3> Comparator Digital Output PIC16F688 C1OUT C2OUT (1) Off C2OUT C2 V ...

  • Page 60

    ... PIC16F688 7.3 Comparator Control The CMCON0 register (Register 7-1) provides access to the following comparator features: • Mode selection • Output state • Output polarity • Input switch 7.3.1 COMPARATOR OUTPUT STATE Each comparator state can always be read internally via the associated CxOUT bit of the CMCON0 register. ...

  • Page 61

    ... See the Comparator and Voltage Reference specifications in Section 14.0 “Electrical Specifications” for more details. © 2006 Microchip Technology Inc. PIC16F688 7.5 Comparator Interrupt Operation The comparator interrupt flag is set whenever there is a change in the output value of the comparator. ...

  • Page 62

    ... PIC16F688 FIGURE 7-6: COMPARATOR INTERRUPT TIMING W/O CMCON0 READ OUT Set CMIF (level) CMIF FIGURE 7-7: COMPARATOR INTERRUPT TIMING WITH CMCON0 READ OUT Set CMIF (level) CMIF cleared by CMCON0 read reset by software Note change in the CM1CON0 register (CxOUT) occurs when a read operation is ...

  • Page 63

    ... Two common reference comparators with outputs 111 = Comparators off. CxIN pins are configured as digital I/O © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 C1INV CIS CM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared - PIC16F688 R/W-0 R/W-0 CM1 CM0 bit Bit is unknown DS41203C-page 61 ...

  • Page 64

    ... PIC16F688 7.8 Comparator C2 Gating Timer1 This feature can be used to time the duration or interval of analog events. Clearing the T1GSS bit of the CMCON1 register will enable Timer1 to increment based on the output of Comparator C2. This requires that Timer1 is on and gating is enabled. See Section 6.0 “Timer1 Module with Gate Control” for details ...

  • Page 65

    ... Voltage Reference can be found in Section 14.0 “Electrical Specifications”. U-0 R/W-0 R/W-0 — VR3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared drain and REF SS VR<3:0> 15) = (VR<3:0>/24 (VR<3:0>/32 PIC16F688 CV OUTPUT VOLTAGE REF = (VR<3:0>/24 (VR<3:0> V /32 / cannot be realized due module current. REF ...

  • Page 66

    ... PIC16F688 FIGURE 7-8: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16-1 Analog MUX VREN REF Comparator 2 Input 1 0 (1) VR<3:0> TABLE 7-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES Name Bit 7 Bit 6 Bit 5 ANSEL ANS7 ANS6 ANS5 CMCON0 C2OUT C1OUT C2INV CMCON1 — ...

  • Page 67

    ... REF RA2/AN2 RA4/AN3 RC0/AN4 RC1/AN5 RC2/AN6 RC3/AN7 © 2006 Microchip Technology Inc. (ADC) allows V DD VCFG = 0 V REF VCFG = 1 000 001 A/D 010 GO/DONE 011 100 ADFM 101 110 ADON 111 V SS CHS PIC16F688 Left Justify 1 = Right Justify 10 ADRESH ADRESL DS41203C-page 65 ...

  • Page 68

    ... PIC16F688 8.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • Port configuration • Channel selection • ADC voltage reference selection • ADC conversion clock source • Interrupt control • Results formatting 8.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals ...

  • Page 69

    ... RC CYCLES ADRESH and ADRESL registers are loaded, GO bit is cleared, ADIF bit is set, Holding capacitor is connected to analog input PIC16F688 ) OSC 4 MHz 1 MHz (2) 500 ns 2.0 s (2) 1.0 s 4.0 s (3) 2.0 s 8.0 s (3) 4.0 s 16.0 s (3) (3) 8.0 s 32.0 s (3) (3) 16.0 s 64.0 s ...

  • Page 70

    ... PIC16F688 8.1.5 INTERRUPTS The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital Conversion. The ADC interrupt flag is the ADIF bit in the PIR1 register. The ADC interrupt enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software ...

  • Page 71

    ... Waiting for the ADC interrupt (interrupts enabled) 7. Read ADC Result 8. Clear the ADC interrupt flag (required if interrupt is enabled). Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: See Section 8.3 Requirements”. RC PIC16F688 (1) (2) . “A/D Acquisition DS41203C-page 69 ...

  • Page 72

    ... PIC16F688 EXAMPLE 8-1: A/D CONVERSION ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL ADCON1 ; MOVLW B’01110000’ ;ADC Frc clock MOVWF ADCON1 ; BANKSEL TRISA ; BSF TRISA,0 ...

  • Page 73

    ... CHS1 CHS0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 U-0 U-0 — — ADCS0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared PIC16F688 R/W-0 R/W-0 GO/DONE ADON bit Bit is unknown U-0 U-0 — — bit Bit is unknown ...

  • Page 74

    ... PIC16F688 REGISTER 8-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x ADRES9 ADRES8 ADRES7 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 8-4: ...

  • Page 75

    ... A P PLIE D 2047 ln(1/2047 10k ln(0.0004885) 50°C- 25°C 0.05µ /° has no effect on the equation, since it cancels itself out not discharged after each conversion. HOLD PIC16F688 5. Temperature Coefficient charged to within 1/2 lsb CHOLD charge response to V CHOLD APPLIED DS41203C-page 73 ...

  • Page 76

    ... PIC16F688 FIGURE 8-4: ANALOG INPUT MODEL ANx Rs C PIN Legend Input Capacitance PIN V = Threshold Voltage Leakage current at the pin due to LEAKAGE various junctions R = Interconnect Resistance Sampling Switch C = Sample/Hold Capacitance HOLD FIGURE 8-5: ADC TRANSFER FUNCTION 3FFh 3FEh 3FDh 3FCh 3FBh 004h ...

  • Page 77

    ... TXIF RA4 RA3 RA2 RA1 RC4 RC3 RC2 RC1 TRISA4 TRISA3 TRISA2 TRISA1 TRISC4 TRISC3 TRISC2 TRISC1 PIC16F688 Value on Value on Bit 0 all other POR, BOR Resets ADON 00-0 0000 00-0 0000 — -000 ---- -000 ---- ANS0 1111 1111 1111 1111 xxxx xxxx ...

  • Page 78

    ... PIC16F688 NOTES: DS41203C-page 76 © 2006 Microchip Technology Inc. ...

  • Page 79

    ... EEPROM memory and read the program memory. When code-protected, the device programmer can no longer access data or program memory. © 2006 Microchip Technology Inc. PIC16F688 9.1 EEADR and EEADRH Registers The EEADR and EEADRH registers can address maximum of 256 bytes of data EEPROM maximum of 4K words of program EEPROM ...

  • Page 80

    ... PIC16F688 REGISTER 9-1: EEDAT: EEPROM DATA REGISTER R/W-0 R/W-0 R/W-0 EEDAT7 EEDAT6 EEDAT5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 EEDATn: Byte Value to Write to or Read from Data EEPROM bits REGISTER 9-2: EEADR: EEPROM ADDRESS REGISTER ...

  • Page 81

    ... Initiates a memory read (the RD is cleared in hardware and can only be set, not cleared, in software Does not initiate a memory read © 2006 Microchip Technology Inc. U-0 R/W-x R/W-0 — WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared PIC16F688 R/S-0 R/S bit Bit is unknown DS41203C-page 79 ...

  • Page 82

    ... PIC16F688 9.1.2 READING THE DATA EEPROM MEMORY To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit of the EECON1 register, and then set control bit RD of the EECON1 register. The data is available in the very next cycle, in the EEDAT register; therefore, it can be read in the next instruction ...

  • Page 83

    ... Byte of Program Address to read ; ;Point to PROGRAM memory ;EE Read ;First instruction after BSF EECON1,RD executes normally ;Any instructions here are ignored as program ;memory is read in second cycle after BSF EECON1, Byte of Program Memory ; ; Byte of Program EEDAT ; ;Bank 0 PIC16F688 instruction on the next DS41203C-page 81 ...

  • Page 84

    ... PIC16F688 FIGURE 9-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Flash ADDR Flash Data INSTR (PC) INSTR( BSF EECON1,RD executed here executed here RD bit EEDATH EEDAT Register EERHLT TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM Name Bit 7 Bit 6 Bit 5 EECON1 EEPGD — ...

  • Page 85

    ... Block diagrams of the EUSART transmitter and receiver are shown in Figure 10-1 and Figure 10-2. Data Bus TXREG Register 8 MSb (8) • • • Transmit Shift Register (TSR) TRMT TX9 x16 x64 TX9D PIC16F688 TXIE Interrupt TXIF TX/CK pin LSb Pin Buffer 0 and Control SPEN DS41203C-page 83 ...

  • Page 86

    ... PIC16F688 FIGURE 10-2: EUSART RECEIVE BLOCK DIAGRAM RX/DT pin Pin Buffer and Control Baud Rate Generator BRG16 + 1 Multiplier SYNC SPBRGH SPBRG BRGH BRG16 The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) • ...

  • Page 87

    ... I/O function must be disabled by clearing the corresponding ANSEL bit. © 2006 Microchip Technology Inc. PIC16F688 Note 1: When the SPEN bit is set, the RX/DT I/O pin is automatically configured as an input, regardless of the state of the corresponding TRIS bit and whether or not the EUSART receiver is enabled ...

  • Page 88

    ... PIC16F688 10.1.1.4 TSR Status The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register ...

  • Page 89

    ... BRG4 BRG3 BRG2 BRG1 BRG12 BRG11 BRG10 BRG9 TRISC4 TRISC3 TRISC2 TRISC1 SYNC SENDB BRGH TRMT PIC16F688 Value on Value on Bit 0 all other POR, BOR Resets ABDEN 01-0 0-00 01-0 0-00 0000 000x 0000 000x RAIF TMR1IE 0000 0000 0000 0000 0000 0000 ...

  • Page 90

    ... PIC16F688 10.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode would typically be used in RS-232 systems. The receiver block diagram is shown in Figure 10-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate ...

  • Page 91

    ... FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. © 2006 Microchip Technology Inc. PIC16F688 10.1.2.7 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems ...

  • Page 92

    ... PIC16F688 10.1.2.8 Asynchronous Reception Set-up: 1. Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 10.3 “EUSART Baud Rate Generator (BRG)”). 2. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation ...

  • Page 93

    ... BRG4 BRG3 BRG2 BRG1 BRG12 BRG11 BRG10 BRG9 TRISC4 TRISC3 TRISC2 TRISC1 SYNC SENDB BRGH TRMT PIC16F688 Value on Value on Bit 0 all other POR, BOR Resets ABDEN 01-0 0-00 01-0 0-00 0000 000x 0000 000x RAIF TMR1IE 0000 0000 0000 0000 0000 0000 ...

  • Page 94

    ... PIC16F688 10.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block out- put (INTOSC). However, the INTOSC frequency may drift temperature changes, and this directly DD affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind ...

  • Page 95

    ... This can be address/data bit or a parity bit and must be calculated by user firmware. © 2006 Microchip Technology Inc. R/W-0 R/W-0 R-0 CREN ADDEN FERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared PIC16F688 (1) R-0 R-x OERR RX9D bit Bit is unknown DS41203C-page 93 ...

  • Page 96

    ... PIC16F688 REGISTER 10-3: BAUDCTL: BAUD RATE CONTROL REGISTER R-0 R-1 U-0 ABDOVF RCIDL — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’ ...

  • Page 97

    ... Bit 3 Bit 2 Bit 1 SCKP BRG16 — WUE CREN ADDEN FERR OERR BRG4 BRG3 BRG2 BRG1 BRG12 BRG11 BRG10 BRG9 SYNC SENDB BRGH TRMT PIC16F688 CALCULATING BAUD RATE ERROR of 16 MHz, desired baud rate OSC -------------------------------------------------------------------- - = 64 [SPBRGH:SPBRG -------------------------------------------- - Desired Baud Rate --------------------------------------------- – 64 16000000 ----------------------- - ...

  • Page 98

    ... PIC16F688 TABLE 10-5: BAUD RATES FOR ASYNCHRONOUS MODES F = 20.000 MHz OSC BAUD SPBRG RATE Actual % Actual value Rate Error (decimal) 300 — — — 1200 1221 1.73 255 2400 2404 0.16 129 9600 9470 -1.36 32 10417 10417 0.00 29 10286 19.2k 19.53k 1 ...

  • Page 99

    ... PIC16F688 F = 1.000 MHz OSC SPBRG SPBRG Actual % value value Rate Error (decimal) (decimal) — 300 0.16 207 103 1202 0. 2404 0. — ...

  • Page 100

    ... PIC16F688 TABLE 10-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 20.000 MHz OSC BAUD SPBRG RATE Actual % Actual value Rate Error (decimal) 300 300.0 0.00 16665 1200 1200 -0.01 4166 2400 2400 0.02 2082 9600 9597 -0 ...

  • Page 101

    ... During the ABD sequence, SPBRG and SPBRGH registers are both used as a 16-bit counter, independent of BRG16 setting. Edge #2 Edge #1 Edge #3 bit 1 bit 3 Start bit 0 bit 2 bit 4 XXh XXh PIC16F688 “Auto-Wake-up on BRG COUNTER CLOCK RATES BRG Base BRG ABD Clock Clock F /64 F /512 OSC OSC ...

  • Page 102

    ... PIC16F688 10.3.2 AUTO-WAKE-UP ON BREAK During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. ...

  • Page 103

    ... Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDCTL register before placing the EUSART in Sleep mode. PIC16F688 Auto Cleared Note 1 DS41203C-page 101 ...

  • Page 104

    ... PIC16F688 FIGURE 10-9: SEND BREAK CHARACTER SEQUENCE Write to TXREG Dummy Write BRG Output (Shift Clock) TX (pin) Start bit TXIF bit (Transmit interrupt Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB Sampled Here SENDB (send Break control bit) DS41203C-page 102 bit 0 ...

  • Page 105

    ... Clock polarity is selected with the SCKP bit of the BAUDCTL register. Setting the SCKP bit sets © 2006 Microchip Technology Inc. PIC16F688 the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock. Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is cleared, the data changes on the rising edge of each clock ...

  • Page 106

    ... PIC16F688 FIGURE 10-10: SYNCHRONOUS TRANSMISSION RX/DT bit 0 bit 1 pin Word 1 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit ‘1’ TXEN bit Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words. ...

  • Page 107

    ... FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. © 2006 Microchip Technology Inc. PIC16F688 10.4.1.8 Synchronous Master Reception Set- up: 1. Initialize the SPBRGH, SPBRG register pair for the appropriate baud rate ...

  • Page 108

    ... PIC16F688 FIGURE 10-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT bit 0 pin TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit ‘0’ CREN bit RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. ...

  • Page 109

    ... OERR BRG4 BRG3 BRG2 BRG1 BRG12 BRG11 BRG10 BRG9 TRISC4 TRISC3 TRISC2 TRISC1 SYNC SENDB BRGH TRMT PIC16F688 Synchronous Slave Transmission Set-up: by writing the Least Value on Value on Bit 0 all other POR, BOR Resets ABDEN 01-0 0-00 01-0 0-00 RAIF 0000 000x ...

  • Page 110

    ... PIC16F688 10.4.2.3 EUSART Synchronous Slave Reception The operation of the Synchronous Master and Slave modes is identical (Section 10.4.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don’t care” in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep ...

  • Page 111

    ... SPECIAL FEATURES OF THE CPU The PIC16F688 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, power-saving features and offer code protection. These features are: • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • ...

  • Page 112

    ... PIC16F688 11.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’) to select various device configurations as shown in Register 11-1. These bits are mapped in program memory location 2007h. Note: Address 2007h is beyond the user program memory space. It belongs to the special ...

  • Page 113

    ... When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. © 2006 Microchip Technology Inc. Reserved FCMEN (4) PWRTE WDTE FOSC2 P = Programmable’ ‘0’ = Bit is cleared (1) (2) (3) DD PIC16F688 (1) (1) IESO BOREN1 BOREN0 bit 8 FOSC1 FOSC0 bit Unimplemented bit, read as ‘0’ Bit is unknown DS41203C-page 111 ...

  • Page 114

    ... PIC16F688 11.2 Reset The PIC16F688 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) WDT Reset during normal operation c) WDT Reset during Sleep d) MCLR Reset during normal operation e) MCLR Reset during Sleep f) Brown-out Reset (BOR) Some registers are not affected in any Reset condition; ...

  • Page 115

    ... For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). 11.2.2 MCLR PIC16F688 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. ...

  • Page 116

    ... PIC16F688 11.2.4 BROWN-OUT RESET (BOR) The BOREN0 and BOREN1 bits in the Configuration Word register selects one of four BOR modes. Two modes have been added to allow software or hardware control of the BOR enable. When BOREN<1:0> = 01, the SBOREN bit of the PCON register enables/disables the BOR, allowing controlled in software. By selecting BOREN< ...

  • Page 117

    ... Then, bringing MCLR high will begin execution immediately (see Figure 11-5). This is useful for testing purposes or to synchronize more than one PIC16F688 device operating in parallel. Table 11-5 shows the Reset conditions for some special registers, while Table 11-4 shows the Reset conditions for all the registers ...

  • Page 118

    ... PIC16F688 FIGURE 11-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 11-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 11-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR ...

  • Page 119

    ... PIC16F688 Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out uuuu uuuu uuuu uuuu uuuu uuuu ( (4) uuuq quuu uuuu uuuu ...

  • Page 120

    ... PIC16F688 TABLE 11-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) Power-on Register Address Reset OSCCON 8Fh -110 q000 OSCTUNE 90h ---0 0000 ANSEL 91h 1111 1111 WPUA 95h --11 -111 IOCA 96h --00 0000 EEDATH 97h --00 0000 EEADRH 98h ---- 0000 VRCON 99h 0-0- 0000 EEDAT 9Ah ...

  • Page 121

    ... Interrupts The PIC16F688 has multiple sources of interrupt: • External Interrupt RA2/INT • TMR0 Overflow Interrupt • PORTA Change Interrupts • 2 Comparator Interrupts • A/D Interrupt • Timer1 Overflow Interrupt • EEPROM Data Write Interrupt • Fail-Safe Clock Monitor Interrupt • EUSART Receive and Transmit interrupts ...

  • Page 122

    ... PIC16F688 11.3.1 RA2/INT INTERRUPT External interrupt on RA2/INT pin is edge-triggered; either rising if the INTEDG bit of the OPTION register is set, or falling if the INTEDG bit is clear. When a valid edge appears on the RA2/INT pin, the INTF bit of the INTCON register is set. This interrupt can be disabled by clearing the INTE control bit of the INTCON register ...

  • Page 123

    ... Inst (PC) . Synchronous latency = where Bit 4 Bit 3 Bit 2 Bit 1 INTE RAIE T0IF INTF C2IE C1IE OSFIE TXIE C2IF C1IF OSFIF TXIF PIC16F688 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) = instruction cycle time. CY Value on Value on Bit 0 all other POR, BOR Resets RAIF ...

  • Page 124

    ... Store the Status register • Execute the ISR code • Restore the Status (and Bank Select Bit register) • Restore the W register Note: The PIC16F688 normally does not require saving the PCLATH. computed GOTO’s are used in the ISR and the main code, the PCLATH must be saved and restored in the ISR ...

  • Page 125

    ... WDT. Setting the bit will enable it and clearing the bit will disable it. The PSA and PS<2:0> bits of the OPTION register have the same function as in previous versions of the PIC16F688 family of microcontrollers. See Section 5.0 “Timer0 Module” for more information. 0 From TMR0 Clock Source ...

  • Page 126

    ... PIC16F688 REGISTER 11-2: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate ...

  • Page 127

    ... SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. PIC16F688 DS41203C-page 125 ...

  • Page 128

    ... PIC16F688 FIGURE 11-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT OSC1 (4) CLKOUT INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) Instruction Flow Instruction Inst( Inst(PC) = Sleep Fetched Instruction Sleep Inst( Executed Note 1: XT Oscillator mode assumed 1024 T (drawing not to scale). This delay does not apply to EC and RC Oscillator modes. ...

  • Page 129

    ... PIC16F688 device. The IHH Programming debugging adapter is the only source of the ICD device. When the ICD pin on the PIC16F688 ICD device is held low, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2. When the microcontroller has this feature enabled, some of the resources are not available for general use ...

  • Page 130

    ... PIC16F688 NOTES: DS41203C-page 128 © 2006 Microchip Technology Inc. ...

  • Page 131

    ... INSTRUCTION SET SUMMARY The PIC16F688 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction ...

  • Page 132

    ... PIC16F688 TABLE 12-2: PIC16F684 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW – Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ ...

  • Page 133

    ... Operands: Operation: Status Affected: Description: BSF Syntax: f,d Operands: Operation: Status Affected: Description: BTFSC Syntax: k Operands: Operation: Status Affected: Description: f,d PIC16F688 Bit Clear f [ label ] BCF f 127 (f<b>) 0 None Bit ‘b’ in register ‘f’ is cleared. Bit Set f [ label ] BSF f 127 ...

  • Page 134

    ... PIC16F688 BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b Operands 127 0 b < 7 Operation: skip if (f<b> Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed. If bit ‘b’ is ‘1’, then the next ...

  • Page 135

    ... The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. © 2006 Microchip Technology Inc. PIC16F688 INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d ...

  • Page 136

    ... PIC16F688 MOVF Move f Syntax: [ label ] MOVF f,d Operands 127 d [0,1] Operation: (f) (dest) Status Affected: Z Description: The contents of register f is moved to a destination dependent upon the status destination is W register the destination is file register f itself useful to test a file register since status flag Z is affected ...

  • Page 137

    ... Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 © 2006 Microchip Technology Inc. PIC16F688 RETLW Return with literal in W Syntax: [ label ] RETLW k Operands 255 Operation: k (W); TOS PC Status Affected: ...

  • Page 138

    ... PIC16F688 RLF Rotate Left f through Carry Syntax: [ label ] RLF f,d Operands 127 d [0,1] Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. ...

  • Page 139

    ... Syntax: Operands: Operation: Status Affected: Description: f<3:0> f<3:0> XORWF Syntax: Operands: Operation: Status Affected: Description: PIC16F688 Exclusive OR literal with W [ label ] XORLW 255 (W) .XOR The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. ...

  • Page 140

    ... PIC16F688 NOTES: DS41203C-page 138 © 2006 Microchip Technology Inc. ...

  • Page 141

    ... MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2006 Microchip Technology Inc. PIC16F688 13.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...

  • Page 142

    ... PIC16F688 13.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PICmicro MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging ...

  • Page 143

    ... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. © 2006 Microchip Technology Inc. PIC16F688 13.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low-cost, ...

  • Page 144

    ... PIC16F688 13.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PICmicro devices in DIP packages pins. ...

  • Page 145

    ... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. © 2006 Microchip Technology Inc. ........................................................................... -0. – ∑ DIS PIC16F688 + 0.3V ∑ {( ∑(V – DS41203C-page 143 ...

  • Page 146

    ... PIC16F688 FIGURE 14-1: PIC16F688 VOLTAGE-FREQUENCY GRAPH, -40°C T +125°C A 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 14-2: HFINTOSC FREQUENCY ACCURACY OVER DEVICE V 125 2.0 2.5 DS41203C-page 144 8 10 Frequency (MHz) ± ...

  • Page 147

    ... DC Characteristics: PIC16F688 -I (Industrial) PIC16F688 -E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. V Supply Voltage DD D001 D001C D001D D002* V RAM Data Retention DR (1) Voltage D003 V V Start Voltage to POR DD ensure internal Power-on Reset signal D004 Rise Rate to ensure VDD DD internal Power-on Reset signal * These parameters are characterized but not tested ...

  • Page 148

    ... PIC16F688 14.2 DC Characteristics: PIC16F688 -I (Industrial) PIC16F688 -E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. (1, 2) D010 Supply Current ( D011* D012 D013* D014 D015 D016* D017 D018 D019 * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...

  • Page 149

    ... DC Characteristics: PIC16F688-I (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. D020 Power-down Base (2) Current D021 D022 D023 D024 D025* D026 D027 * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...

  • Page 150

    ... PIC16F688 14.4 DC Characteristics: PIC16F688-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. D020E Power-down Base (2) Current ( D021E D022E D023E D024E D025E* D026E D027E * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...

  • Page 151

    ... Higher leakage current may be measured at different input voltages. 4: See Section 9.0 “Data EEPROM and Flash Program Memory Control” for additional information. 5: Including OSC2 in CLKOUT mode. © 2006 Microchip Technology Inc. PIC16F688 -I (Industrial) PIC16F688 -E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C -40°C Min Typ† ...

  • Page 152

    ... Higher leakage current may be measured at different input voltages. 4: See Section 9.0 “Data EEPROM and Flash Program Memory Control” for additional information. 5: Including OSC2 in CLKOUT mode. DS41203C-page 150 PIC16F688 -I (Industrial) PIC16F688 -E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C -40°C Min Typ† ...

  • Page 153

    ... QFN 4x0.9mm package 32.5 C/W 14-pin PDIP package 31.0 C/W 14-pin SOIC package 31.7 C/W 14-pin TSSOP package 2.6 C/W 16-pin QFN 4x0.9mm package 150 C For derated power calculations — — INTERNAL (NOTE 1) — — DER (NOTE DER PIC16F688 Conditions + P / INTERNAL DS41203C-page 151 ...

  • Page 154

    ... PIC16F688 14.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings CCP1 ck CLKOUT SDI do SDO dt Data in io I/O PORT mc MCLR Uppercase letters and their meanings Fall ...

  • Page 155

    ... AC Characteristics: PIC16F688 (Industrial, Extended) FIGURE 14-4: CLOCK TIMING Q4 OSC1/CLKIN OSC2/CLKOUT (LP, XT, HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 14-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C T Param Sym Characteristic No. OS01 F External CLKIN Frequency OSC (1) Oscillator Frequency ...

  • Page 156

    ... PIC16F688 TABLE 14-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40° Param Sym Characteristic No. OS06 T Internal Oscillator Switch WARM (3) when running OS07 T Fail-Safe Sample Clock SC (1) Period OS08 HF Internal Calibrated OSC HFINTOSC Frequency OS09* LF Internal Uncalibrated OSC LFINTOSC Frequency ...

  • Page 157

    ... OS16 OS13 OS17 OS15 OS18, OS19 +125°C Min (1) — (1) — (1) — ( 200 ns OSC — 50 (Q2 cycle) 20 OSC (2) — — (2) — — PIC16F688 Execute Q3 OS12 OS18 OS14 New Value Typ† Max Units Conditions — 5.0V DD — 5.0V DD — — — ...

  • Page 158

    ... PIC16F688 FIGURE 14-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING V DD MCLR Internal POR 33 PWRT Time-out OSC Start-Up Time (1) Internal Reset Watchdog Timer (1) Reset I/O pins Note 1: Asserted low. FIGURE 14-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS BOR (Device in Brown-out Reset) ...

  • Page 159

    ... All specified values and V must be capacitively decoupled as close to the device PIC16F688 Conditions 5V, -40°C to +85° 5V, -40°C to +85° ...

  • Page 160

    ... PIC16F688 FIGURE 14-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI T1CKI TMR0 or TMR1 TABLE 14-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40° Param Sym Characteristic No. 40 T0CKI High Pulse Width T 41 T0CKI Low Pulse Width ...

  • Page 161

    ... SPECIFICATIONS REF +125°C Min Typ† Max — — V /24 DD — V /32 — DD — — 1/2 — — 1/2 — 2k — — — 10 PIC16F688 Max Units Comments 1.5)/ – 1 — dB 600 ns (NOTE 1) 1000 1.5)/ mV. DD Units Comments V Low Range (VRR = 1) ...

  • Page 162

    ... PIC16F688 TABLE 14-8: PIC16F688 A/D CONVERTER (ADC) CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40° Param Sym Characteristic No. AD01 N Resolution R AD02 E Integral Error IL AD03 E Differential Error DL AD04 E Offset Error OFF AD07 E Gain Error GN (1) AD06 V Reference Voltage REF AD06A ...

  • Page 163

    ... TABLE 14-9: PIC16F688 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40° Param Sym Characteristic No. AD130* T A/D Clock Period AD A/D Internal RC Oscillator Period AD131 T Conversion Time CNV (not including (1) Acquisition Time) AD132* T Acquisition Time ACQ AD133* T Amplifier Settling Time ...

  • Page 164

    ... OSC Q4 A/D CLK A/D Data ADRES ADIF GO AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. FIGURE 14-10: PIC16F688 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 ( OSC Q4 A/D CLK A/D Data ADRES ADIF GO ...

  • Page 165

    ... MHz 2 MHz 4 MHz © 2006 Microchip Technology Inc. vs. F OVER V (EC MODE) OSC DD 6 MHz 8 MHz 10 MHz 12 MHz F OSC PIC16F688 5.5V 5.0V 4.0V 3.0V 2.0V 14 MHz 16 MHz 18 MHz 20 MHz DS41203C-page 1 DD ...

  • Page 166

    ... Microchip Technology Inc. vs. F OVER V (EC MODE) OSC DD EC Mode 6 MHz 8 MHz 10 MHz 12 MHz F OSC vs. F OVER V (HS MODE) OSC DD HS Mode 4.0V 3.5V 3.0V 10 MHz 16 MHz F OSC PIC16F688 5.5V 5.0V 4.0V 3.0V 2.0V 14 MHz 16 MHz 18 MHz 20 MHz 5.5V 5,0V 4.5V 20 MHz DS41203C-page 2 ...

  • Page 167

    ... Microchip Technology Inc. vs. F OVER V (HS MODE) OSC DD HS Mode 4.0V 3.5V 3.0V 10 MHz 16 MHz F OSC vs. V OVER F (XT MODE) DD OSC XT Mode 4 MHz 1 MHz 3 3 (V) DD PIC16F688 5.5V 5.0V 4.5V 20 MHz 4.5 5 5.5 DS41203C-page 3 ...

  • Page 168

    ... Microchip Technology Inc. vs. V OVER F (XT MODE) DD OSC XT Mode 4 MHz 1 MHz 3 3 (V) DD vs. V OVER F (EXTRC MODE) DD OSC 4 MHz 1 MHz 3 3 (V) DD PIC16F688 4.5 5 5.5 4.5 5 5.5 DS41203C-page 4 ...

  • Page 169

    ... Maximum: Mean (Worst-case Temp (-40°C to 125° 2.0 2.5 © 2006 Microchip Technology Inc. vs. V (EXTRC MODE) DD EXTRC Mode 4 MHz 1 MHz 3 3 (V) DD (LFINTOSC MODE, 31 kHz) OSC LFINTOSC Mode, 31KHZ Maximum Typical 3.0 3.5 4.0 V (V) DD PIC16F688 4.5 5 5.5 4.5 5.0 5.5 DS41203C-page 5 ...

  • Page 170

    ... Microchip Technology Inc. LP Mode 32 kHz Maximum 32 kHz Typical 3 3 (V) DD vs. F OVER V (HFINTOSC MODE) OSC DD HFINTOSC 500 kHz 1 MHz 2 MHz V (V) DD PIC16F688 4.5 5 5.5 5.5V 5.0V 4.0V 3.0V 2.0V 4 MHz 8 MHz DS41203C-page 6 ...

  • Page 171

    ... Microchip Technology Inc. vs. F OVER V (HFINTOSC MODE) OSC DD 500 kHz 1 MHz 2 MHz V (V) DD vs. V (SLEEP MODE, ALL PERIPHERALS DISABLED) DD Typical (Sleep Mode all Peripherals Disabled) 3.0 3.5 4.0 V (V) DD PIC16F688 5.5V 5.0V 4.0V 3.0V 2.0V 4 MHz 8 MHz 4.5 5.0 5.5 DS41203C-page 7 ...

  • Page 172

    ... Microchip Technology Inc. vs. V (SLEEP MODE, ALL PERIPHERALS DISABLED) DD Maximum (Sleep Mode all Peripherals Disabled) Max. 125°C Max. 85°C 3.0 3.5 4.0 V (V) DD vs. V (BOTH COMPARATORS ENABLED Maximum Typical 3.0 3.5 4.0 V (V) DD PIC16F688 4.5 5.0 5.5 4.5 5.0 5.5 DS41203C-page 8 ...

  • Page 173

    ... FIGURE 15-17: TYPICAL WDT I 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.0V 2.5V © 2006 Microchip Technology Inc. OVER TEMPERATURE DD Maximum Typical 3.5 4.0 4.5 V (V) DD vs. V (25° 3.0V 3.5V 4.0V V (V) DD PIC16F688 5.0 5.5 4.5V 5.0V 5.5V DS41203C-page 9 ...

  • Page 174

    ... Microchip Technology Inc. vs. V OVER TEMPERATURE PD DD Max. 125°C Max. 85°C 3.0V 3.5V 4.0V V (V) DD OVER TEMPERATURE DD Max. (125°C) Max. (85°C) Typical Minimum 3.0 3.5 4.0 V (V) DD PIC16F688 4.5V 5.0V 5.5V 4.5 5.0 5.5 DS41203C-page 10 ...

  • Page 175

    ... Maximum: Mean + 3 (-40°C to 125°C) 120 100 2.0 2.5 © 2006 Microchip Technology Inc. Vdd = 5V Maximum Typical Minimum 25°C 85°C Temperature (°C) OVER TEMPERATURE (HIGH RANGE) DD High Range Max. 125°C Max. 85°C Typical 3.0 3.5 4.0 V (V) DD PIC16F688 125°C 4.5 5.0 5.5 DS41203C-page 11 ...

  • Page 176

    ... OVER TEMPERATURE (LOW RANGE) DD Max. 125°C Max. 85°C Typical 3.0 3.5 4 3.0V) DD (VDD = 3V, -40×C TO 125×C) Typical 25°C Min. -40°C 6.5 7.0 7.5 8.0 I (mA) OL PIC16F688 4.5 5.0 5.5 Max. 125°C Max. 85°C 8.5 9.0 9.5 10.0 DS41203C-page 12 ...

  • Page 177

    ... Microchip Technology Inc. = 5.0V) DD Max. 125°C Max. 85°C Typ. 25°C Min. -40°C 6.5 7.0 7.5 8.0 8.5 I (mA 3.0V) DD -1.5 -2.0 -2.5 I (mA) OH PIC16F688 9.0 9.5 10.0 Max. -40°C Typ. 25°C Min. 125°C -3.0 -3.5 -4.0 DS41203C-page 13 ...

  • Page 178

    ... I (mA) OH vs. V OVER TEMPERATURE IN DD (TTL Input, -40×C TO 125×C) Max. -40°C Typ. 25°C Min. 125°C 3.0 3.5 4.0 V (V) DD PIC16F688 Max. -40°C Typ. 25°C Min. 125°C -4.0 -4.5 -5.0 4.5 5.0 5.5 DS41203C-page 14 ...

  • Page 179

    ... Input, -40×C TO 125×C) 3.0 3.5 4.0 V (V) DD OVER TEMPERATURE (32 kHz) DD Max. 125°C Max. 85°C Typ. 25°C 3.0 3.5 4.0 V (V) DD PIC16F688 OVER TEMPERATURE DD V Max. 125° Min. -40° Max. -40° Min. 125°C IL 4.5 5.0 5.5 4.5 5 ...

  • Page 180

    ... V- input = Transition from V 400 300 200 100 0 2.0 © 2006 Microchip Technology Inc. + 100 2.5 4 100 2.5 4.0 V (V) DD PIC16F688 Max. 125°C Max. 85°C Typ. 25°C Min. -40°C 5.5 Max. 125°C Max. 85°C Typ. 25°C Min. -40°C 5.5 DS41203C-page 16 ...

  • Page 181

    ... Min. 125°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp (-40°C to 125°C) 3.0 3.5 4.0 V (V) DD OVER TEMPERATURE DD Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp (-40°C to 125°C) 3.0 3.5 4.0 4.5 V (V) DD PIC16F688 4.5 5.0 5.5 5.0 5.5 DS41203C-page 17 ...

  • Page 182

    ... OVER TEMPERATURE DD Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp (-40°C to 125°C) 3.5 4.0 4.5 V (V) DD OVER TEMPERATURE DD -40C to +85C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp (-40°C to 125°C) 3.5 4.0 4.5 V (V) DD PIC16F688 5.0 5.5 5.0 5.5 DS41203C-page 18 ...

  • Page 183

    ... TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 © 2006 Microchip Technology Inc. OVER TEMPERATURE DD -40C to +85C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp (-40°C to 125°C) 3.5 4.0 V (V) DD 3.0 3.5 4.0 V (V) DD PIC16F688 4.5 5.0 5.5 (25°C) DD 4.5 5.0 5.5 DS41203C-page 19 ...

  • Page 184

    ... FIGURE 15-38: TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE 2.0 2.5 FIGURE 15-39: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 © 2006 Microchip Technology Inc. 3.0 3.5 4.0 V (V) DD 3.0 3.5 4.0 V (V) DD PIC16F688 (85°C) DD 4.5 5.0 5.5 (125°C) DD 4.5 5.0 5.5 DS41203C-page 20 ...

  • Page 185

    ... FIGURE 15-40: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 © 2006 Microchip Technology Inc. 3.0 3.5 4.0 4.5 V (V) DD PIC16F688 (-40°C) DD 5.0 5.5 DS41203C-page 21 ...

  • Page 186

    ... NOTES: © 2006 Microchip Technology Inc. PIC16F688 DS41203C-page 22 ...

  • Page 187

    ... For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2006 Microchip Technology Inc. PIC16F688 Example PIC16F688-I/P 0510017 Example PIC16C688 -I/SL ...

  • Page 188

    ... PIC16F688 16.2 Package Details The following sections give the technical details of the packages. 14-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width ...

  • Page 189

    ... L .016 .033 .050 .008 .009 .010 B .014 .017 .020 PIC16F688 A2 MILLIMETERS MIN NOM MAX 14 1.27 1.35 1.55 1.75 1.32 1.42 1.55 0.10 0.18 0.25 5.79 5.99 6.20 3.81 3.90 3.99 8.56 8.69 8.81 0.25 0.38 ...

  • Page 190

    ... PIC16F688 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body (TSSOP Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top ...

  • Page 191

    ... E2 .090** – .110 D .152 .157 .163 D2 .090 – .110 b .010 .012 .014 L .012 .016 .020 K .008 – – PIC16F688 BOTTOM VIEW MILLIMETERS* MIN NOM MAX 16 0.65 BSC 0.80 0.90 1.00 0.00 0.02 0.05 0.20 REF 3.85 4.00 4.15 2.29** – ...

  • Page 192

    ... PIC16F688 NOTES: DS41203C-page 190 © 2006 Microchip Technology Inc. ...

  • Page 193

    ... Microchip Technology Inc. PIC16F688 APPENDIX B: MIGRATING FROM OTHER PICmicro DEVICES This discusses some of the issues in migrating from other PICmicro devices to the PIC16F6XX family of devices. B.1 PIC16F676 to PIC16F688 TABLE B-1: FEATURE COMPARISON Feature PIC16F676 Max Operating Speed 20 MHz Max Program Memory 1024 (Words) ...

  • Page 194

    ... PIC16F688 NOTES: DS41203C-page 192 © 2006 Microchip Technology Inc. ...

  • Page 195

    ... EUSART Receive ....................................................... 84 EUSART Transmit ...................................................... 83 External RC Mode....................................................... 25 Fail-Safe Clock Monitor (FSCM) ................................. 31 In-Circuit Serial Programming Connections.............. 127 Interrupt Logic ........................................................... 120 MCLR Circuit............................................................. 113 On-Chip Reset Circuit ............................................... 112 PIC16F688.................................................................... 5 RA1 Pins ..................................................................... 38 RA2 Pin....................................................................... 38 RA3 Pin....................................................................... 39 RA4 Pin....................................................................... 39 © 2006 Microchip Technology Inc. PIC16F688 RA5 Pin ...................................................................... 40 RC0 and RC1 Pins ...

  • Page 196

    ... PIC16F688 Effects of a Reset........................................................ 60 Specifications ............................................................ 159 CONFIG Register.............................................................. 111 Configuration Bits.............................................................. 110 CPU Features ................................................................... 109 Customer Change Notification Service ............................. 197 Customer Notification Service........................................... 197 Customer Support ............................................................. 197 D Data EEPROM Memory ...................................................... 77 Associated Registers .................................................. 82 Reading....................................................................... 80 Writing ......................................................................... 80 Data Memory......................................................................... 7 DC and AC Characteristics Graphs and Tables ................................................... 163 DC Characteristics Extended and Industrial ...

  • Page 197

    ... Computed GOTO........................................................ 19 © 2006 Microchip Technology Inc. PIC16F688 Stack........................................................................... 19 PCON Register ........................................................... 18, 115 PICSTART Plus Development Programmer..................... 142 PIE1 Register ..................................................................... 16 Pin Diagram ...................................................................... 2, 3 Pinout Description PIC16F688 ................................................................... 6 PIR1 Register ..................................................................... 17 PORTA ............................................................................... 33 Additional Pin Functions ............................................. 34 ANSEL Register ................................................. 34 Interrupt-on-Change ........................................... 34 Ultra Low-Power Wake-up............................ 34, 36 Weak Pull-up ...................................................... 34 Associated registers ................................................... 41 Pin Descriptions and Diagrams ...

  • Page 198

    ... PIC16F688 IOCA (Interrupt-on-Change PORTA) .......................... 35 OPTION_REG (OPTION) ........................................... 14 OPTION_REG (Option) .............................................. 47 OSCCON (Oscillator Control) ..................................... 22 OSCTUNE (Oscillator Tuning) .................................... 26 PCON (Power Control Register) ................................. 18 PCON (Power Control) ............................................. 115 PIE1 (Peripheral Interrupt Enable 1) ........................... 16 PIR1 (Peripheral Interrupt Register 1) ........................ 17 PORTA........................................................................ 33 PORTC ....................................................................... 42 RCSTA (Receive Status and Control)......................... 93 Reset Values............................................................. 117 Reset Values (Special Registers) ...

  • Page 199

    ... Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com PIC16F688 should contact their distributor, DS41203C-page 197 ...

  • Page 200

    ... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC16F688 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...