DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 32

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 7-1. DS33R41 400-Ball BGA Pinout
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
RSYSCLK1
RMSYNC1
RFSYNC1
RCLKO3
RRING1
TRING3
TRING1
TRING1
RCLK3
TTIP3
RTIP1
TTIP1
TTIP1
DV
TV
DV
RV
RV
TV
V
1
SS
DD
SS
SS
SS
SS
DD
TSSYNC3
RCHCLK1
TSYNC3
TSTRST
RSYNC1
TRING3
TSERI3
MCLK1
LOTC1
TSIG3
RLOS/
TTIP3
TVDD
DV
TV
RV
RV
TV
TV
TV
TV
2
SS
SS
SS
DD
DD
SS
SS
SS
RMSYNC3
TCHCLK3
RCHBLK1
TCHCLK1
TCHBLK3
RSYNC3
TNEGO3
RPOSO1
TPOSO1
TCLKO3
TCLKT3
BPCLK1
TSYNC1
RSIG1
DV
DV
DV
N.C.
N.C.
V
3
SS
SS
SS
SS
TSYSCLK1
RCHCLK3
RFSYNC3
RCHBLK3
TCHBLK1
TSSYNC1
RSERO1
RNEGO1
TNEGO1
TPOSO3
TCLKO1
RCLKO1
TCLKT1
TSERI1
RLOS/
LOTC3
DV
DV
N.C.
V
V
4
SS
SS
DD
SS
DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
TSYSCLK2
TSYSCLK4 RSYSCLK4
RPOSO3
RSERO3
RCLK1
RSIG3
TSIG1
N.C.
RV
RV
DV
DV
DV
DV
DV
V
V
V
V
V
5
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
RSYSCLK3
TSYSCLK3
RNEGO4
RRING3
TSYNC4
RTIP3
DV
RV
DV
DV
DV
DV
CST
TPD
V
V
V
V
V
6
SS
SS
SS
SS
SS
DD
SS
SS
SS
SS
SS
MODEC[0]
RCHCLK4
RNEGO3
RPOSO4
RSERO4
TSERI4
RCLK4
TSIG4
JTDI2
RV
N.C.
N.C.
TV
TV
V
V
V
V
V
V
7
SS
SS
SS
SS
SS
SS
DD
SS
SS
RCHBLK4
BPCLK2
RCLK2
LOTC4
TSIG2
RSIG4
RLOS/
TTIP4
TTIP4
DV
DV
DV
DV
DV
RV
RV
N.C.
V
V
V
V
8
SS
SS
SS
SS
DD
DD
DD
SS
SS
DD
SS
RMSYNC4
TCHCLK4
RNEGO2
RSERO2
RSYNC4
TCLKT2
TCLKT4
JTCLK2
RRING4
TRING4
TRING4
TSERI2
RTIP4
DV
DV
DV
DV
DV
V
V
9
SS
SS
DD
DD
DD
DD
SS
32 of 335
RSYSCLK2
RFSYNC4
RPOSO2
TNEGO4
RCLKO4
JTDO2
DV
DV
DV
DV
TV
TV
DV
RV
RV
DV
DV
TV
TV
10
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SDATA[13] SDATA[14]
SDATA[15]
SDATA[11] SDATA[10]
TCHBLK4
SDATA[0]
SDATA[2]
TPOSO4
TCLKO2
TCLKO4
TRING2
TRING2
RSIG2
JTMS2
DV
DV
DV
RV
N.C.
11
V
V
SS
SS
DD
DD
SS
SS
SDATA[12]
SDATA[4]
SDATA[9]
TNEGO2
RCLKO2
TPOSO2
RRING2
MCLK2
TTIP2
TTIP2
DV
RV
N.C.
12
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SDMASK[0]
RMSYNC2
TSSYNC2
TSSYNC4
TCHCLK2
SDATA[6]
SDATA[5]
SDATA[8]
SDATA[7]
RMIIMIIS
JTRST2
TSYNC2
JTMS1
RTIP2
V
TV
TV
RV
13
V
V
DD1.8
SS
SS
SS
SS
SS
SDMASK[1]
TCHBLK2
RCHBLK2
RCHCLK2
RFSYNC2
SDATA[3]
JTRST1
SYSCLKI
SDCLKO
LOTC2
JTDO1
TCLKE
RLOS/
RCLKI
SCAS
RV
V
V
V
14
V
V
DD1.8
DD1.8
DD1.8
SS
SS
DD
MODEC[1]
SDATA[1]
RSYNC2
RBSYNC
RD/DS
TSERO
SDCS
SDA[9]
SRAS
SBA[1]
SWE
V
V
RST
INT
15
V
V
V
D6
D7
DD1.8
DD1.8
SS
SS
SS
WR/RW
TBSYNC
SDA[11]
RSERI
SBA[0]
SDA[8]
SDA[1]
SDA[7]
SDA[5]
SDA[6]
V
V
V
V
16
CS
V
DD3.3
A9
D5
D4
D3
DD3.3
DD1.8
DD1.8
SS
SDMASK[3] SDATA[30] SDATA[22]
DCEDTES
SDA[10]
JTCLK1
SDA[0]
SDA[4]
SDA[3]
SDA[2]
JTDI1
V
V
V
V
N.C.
17
D1
A7
A8
A6
D2
D0
DD3.3
DD1.8
DD1.8
DD1.8
SDMASK[2] SDATA[18] SDATA[19]
SDATA[31]
SDATA[16] SDATA[27] SDATA[26]
SDATA[29] SDATA[25] SDATA[24]
SDATA[17] SDATA[20] SDATA[23]
TX_CLK
RXD[1]
RXD[2]
RX_DV
TXD[2]
QOVF
V
V
V
18
V
A5
A3
A2
DD3.3
A4
DD3.3
DD1.8
SS
REF_CLKO
SDATA[28] SDATA[21]
RX_CRS/
RX_CLK
CRS_DV
RXD[3]
RXD[0]
TX_EN
TXD[1]
V
V
V
V
V
19
V
A0
DD3.3
DD3.3
DD3.3
DD3.3
DD3.3
SS
COL_DET
REF_CLK
RX_ERR
TXD[0]
TXD[3]
MDIO
V
V
V
V
MDC
20
A1
V
V
V
DD3.3
DD3.3
DD1.8
DD1.8
SS
SS
SS