DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 96

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
10.18 Legacy FDL Support (T1 Mode)
10.18.1 Overview
To provide backward compatibility to the older DS21x52 T1 device, the transceiver maintains the circuitry that
existed in the previous generation of the T1 framer. In new applications, it is recommended that the HDLC
controllers and BOC controller described in Section
10.14
and
10.17
are used.
10.18.2 Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the receive FDL register
(TR.RFDL). Because the TR.RFDL is 8 bits in length, it fills up every 2ms (8 x 250μs). The framer signals an
external microcontroller that the buffer has filled through the TR.SR8.3 bit. If enabled through TR.IMR8.3, the INT
pin toggles low, indicating that the buffer has filled and needs to be read. The user has 2ms to read this data
before it is lost. If the byte in the TR.RFDL matches either of the bytes programmed into the TR.RFDLM1 or
TR.RFDLM2 registers, then the TR.SR8.1 bit is set to a 1 and the INT pin toggles low if enabled through
TR.IMR8.1. This feature allows an external microcontroller to ignore the FDL or Fs pattern until an important event
occurs.
The framer also contains a zero destuffer, which is controlled through the TR.T1RCR2.3 bit. In both ANSI T1.403
and TR54016, communications on the FDL follows a subset of an LAPD protocol. The LAPD protocol states that
no more than five 1s should be transmitted in a row so that the data does not resemble an opening or closing flag
(01111110) or an abort signal (11111111). If enabled through TR.T1RCR2.3, the device automatically looks for five
1s in a row, followed by a 0. If it finds such a pattern, it automatically removes the zero. If the zero destuffer sees
six or more 1s in a row followed by a 0, the 0 is not removed. The TR.T1RCR2.3 bit should always be set to a 1
when the device is extracting the FDL. Refer to Application Note 335: DS2141A, DS2151 Controlling the FDL for
information about using the device in FDL applications in this legacy support mode.
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