DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 45

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.8.1
Link aggregation requires an external host microprocessor to issue instructions and to monitor the IMUX function of
the device. The host microprocessor is responsible for the following tasks to open a transmit channel:
The host microprocessor is also responsible for the following tasks to open a receive channel:
When in the data phase, if any of the links are detected to be out of frame (OOF), data will be corrupted. The link
initialization procedure must be initiated again. Note that the serial HDLC or X.86 encoded data is sent on 4 T1/E1
links, each link will not have separate HDLC/X.86 encoded data. The HDLC/X.86 encoding and decoding is data is
only available when the device has performed IMUX function. Hence on the line the FCS for a given HDLC packet
could transport on a separate link than the HDLC data.
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Microprocessor Requirements
Configuring
Issuing a link start command through GL.IMXC.
Monitoring the ITSYNC1-4 status from
Monitoring GL.IMXDFDELS.IDDELS0 to ensure that differential delay is not larger than 7.75ms.
Setting GL.IMXCN.SENDE to begin transmitting data after all links are synchronized.
Resetting the queue pointers in GL.C1QPR.
Monitoring the TOOFLS1-4 status from
Monitoring the status of IRSYNC1-4 and setting GL.IMXCN.RXE to receive data.
GL.IMXCN
to control the links participating in the aggregation.
GL.IMXSS
GL.IMXOOFLS
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or GL.IMXSLS.
to restart handshaking procedure if needed.