PIC18F2510-I/ML Microchip Technology Inc., PIC18F2510-I/ML Datasheet - Page 172

• Manufacturer Part Number: PIC18F2510-I/ML
• Description: Microcontroller; 32 KB Flash; 1024 RAM; 0 EEPROM; 21 I/O; 28-Pin-QFN
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2510-I/ML

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F45J10 FAMILY
15.4.6
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPxCON1 and by setting
the SSPEN bit. In Master mode, the SCLx and SDAx
lines are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I
set, or the bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I
Stop bit conditions.
Once Master mode is enabled, the user has six
options.
1.
2.
3.
4.
5.
6.
FIGURE 15-16:
DS39682B-page 170
SDAx
SCLx
Assert a Start condition on SDAx and SCLx.
Assert a Repeated Start condition on SDAx and
SCLx.
transmission of data/address.
Configure the I
Generate an Acknowledge condition at the end
of a received byte of data.
Generate a Stop condition on SDAx and SCLx.
Write to the SSPxBUF register initiating
MASTER MODE
2
C bus operations based on Start and
2
C bus may be taken when the P bit is
2
C port to receive data.
MSSP BLOCK DIAGRAM (I
SDAx In
SCLx In
Bus Collision
Read
MSb
Write Collision Detect
End of XMIT/RCV
Start bit, Stop bit,
State Counter for
Clock Arbitration
Acknowledge
Start bit Detect
Stop bit Detect
SSPxBUF
SSPxSR
Generate
Preliminary
2
C™ MASTER MODE)
LSb
Write
The following events will cause the MSSP Interrupt
Flag bit, SSPxIF, to be set (and MSSP interrupt, if
enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
Clock
Data Bus
Shift
Note:
Internal
Set/Reset S, P, WCOL (SSPxSTAT, SSPxCON1)
Set SSPxIF, BCLxIF
Reset ACKSTAT, PEN (SSPxCON2)
The MSSP module, when configured in
I
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register to
initiate transmission before the Start con-
dition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPxBUF did not occur.
2
C Master mode, does not allow queueing
© 2006 Microchip Technology Inc.
SSPM3:SSPM0
SSPxADD<6:0>
Generator
Baud
Rate