PIC18F2510-I/ML Microchip Technology Inc., PIC18F2510-I/ML Datasheet - Page 239

• Manufacturer Part Number: PIC18F2510-I/ML
• Description: Microcontroller; 32 KB Flash; 1024 RAM; 0 EEPROM; 21 I/O; 28-Pin-QFN
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2510-I/ML

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

20.4
The Two-Speed Start-up feature helps to minimize the
latency period, from oscillator start-up to code execu-
tion, by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
configuration bit.
Two-Speed Start-up should be enabled only if the
primary oscillator mode is HS (Crystal-based) modes.
Since the EC mode does not require an OST start-up
delay, Two-Speed Start-up should be disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the inter-
nal oscillator block as the clock source, following the
time-out of the Power-up Timer after a POR Reset is
enabled. This allows almost immediate code execution
while the primary oscillator starts and the OST is
running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
FIGURE 20-3:
© 2006 Microchip Technology Inc.
Two-Speed Start-up
Note 1:
CPU Clock
Peripheral
Program
INTOSC
Counter
OSC1
Clock
T
Wake from Interrupt Event
OST
TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC)
= 1024 T
PC
OSC
. These intervals are not shown to scale.
Q1
T
OST
(1)
Q2
PC + 2
OSTS bit Set
Preliminary
Q3
Q4
PIC18F45J10 FAMILY
In all other power-managed modes, Two-Speed
Start-up is not used. The device will be clocked by the
currently selected clock source until the primary clock
source becomes available. The setting of the IESO bit
is ignored.
20.4.1
While using the INTRC oscillator in Two-Speed
Start-up, the device still obeys the normal command
sequences for entering power-managed modes,
including
Section 3.1.4 “Multiple Sleep Commands”). In
practice, this means that user code can change the
SCS1:SCS0 bit settings or issue SLEEP instructions
before the OST times out. This would allow an applica-
tion to briefly wake-up, perform routine “housekeeping”
tasks and return to Sleep before the device starts to
operate from the primary oscillator.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator block is providing the clock during
wake-up from Reset or Sleep mode.
Q1
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
serial
PC + 4
SLEEP
Q2
Q3 Q4
instructions
Q1
PC + 6
DS39682B-page 237
Q2
Q3
(refer
to