PIC18F2510-I/ML Microchip Technology Inc., PIC18F2510-I/ML Datasheet - Page 183

• Manufacturer Part Number: PIC18F2510-I/ML
• Description: Microcontroller; 32 KB Flash; 1024 RAM; 0 EEPROM; 21 I/O; 28-Pin-QFN
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2510-I/ML

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.4.17.1
During a Start condition, a bus collision occurs if:
a)
b)
During a Start condition, both the SDAx and the SCLx
pins are monitored.
If the SDAx pin is already low, or the SCLx pin is
already low, then all of the following occur:
• the Start condition is aborted;
• the BCLxIF flag is set; and
• the MSSP module is reset to its Idle state
The Start condition begins with the SDAx and SCLx
pins deasserted. When the SDAx pin is sampled high,
the
SSPxADD<6:0> and counts down to ‘0’. If the SCLx pin
is sampled low while SDAx is high, a bus collision
occurs, because it is assumed that another master is
attempting to drive a data ‘1’ during the Start condition.
FIGURE 15-26:
© 2006 Microchip Technology Inc.
(Figure 15-26).
SDAx
SCLx
SEN
BCLxIF
S
SSPxIF
SDAx or SCLx are sampled low at the beginning
of the Start condition (Figure 15-26).
SCLx is sampled low before SDAx is asserted
low (Figure 15-27).
Baud
Bus Collision During a Start
Condition
Rate
condition if SDAx = 1, SCLx = 1
Set SEN, enable Start
Generator
BUS COLLISION DURING START CONDITION (SDAx ONLY)
SDAx sampled low before
Start condition. Set BCLxIF.
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
SDAx goes low before the SEN bit is set.
Set BCLxIF,
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
is
loaded
from
Preliminary
SSPxIF and BCLxIF are
cleared in software
PIC18F45J10 FAMILY
If the SDAx pin is sampled low during this count, the
BRG is reset and the SDAx line is asserted early
(Figure 15-28). If, however, a ‘1’ is sampled on the
SDAx pin, the SDAx pin is asserted low at the end of
the BRG count. The Baud Rate Generator is then
reloaded and counts down to ‘0’. If the SCLx pin is
sampled as ‘0’ during this time, a bus collision does not
occur. At the end of the BRG count, the SCLx pin is
asserted low.
Note:
SEN cleared automatically because of bus collision.
MSSP module reset into Idle state.
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDAx before the other.
This condition does not cause a bus colli-
sion because the two masters must be
allowed to arbitrate the first address
following the Start condition. If the address
is the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
SSPxIF and BCLxIF are
cleared in software
DS39682B-page 181