PIC16LF1827-I/MV Microchip Technology Inc., PIC16LF1827-I/MV Datasheet - Page 185

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PIC16LF1827-I/MV

Manufacturer Part Number
PIC16LF1827-I/MV
Description
7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, nan
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC16LF1827-I/MV

A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
8 MIPS
Eeprom Memory
256 Bytes
Input Output
16
Interface
CAN/I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin SOIC
Programmable Memory
7K Bytes
Ram Size
384 Bytes
Speed
32 MHz
Timers
4-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V

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21.11 Timer1 Control Register
The Timer1 Control register (T1CON), shown in
Register
various features of the Timer1 module.
REGISTER 21-1:
 2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 5-4
bit 3
bit 2
bit 1
bit 0
R/W-0/u
TMR1CS<1:0>
21-1, is used to control Timer1 and select the
TMR1CS<1:0>: Timer1 Clock Source Select bits
11 = Timer1 clock source is Capacitive Sensing Oscillator (CAPOSC)
10 = Timer1 clock source is pin or oscillator:
01 = Timer1 clock source is system clock (F
00 = Timer1 clock source is instruction clock (F
T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
T1OSCEN: LP Oscillator Enable Control bit
1 = Dedicated Timer1 oscillator circuit enabled
0 = Dedicated Timer1 oscillator circuit disabled
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS<1:0> = 1X:
1 = Do not synchronize external clock input
0 = Synchronize external clock input with system clock (F
TMR1CS<1:0> = 0X:
This bit is ignored.
Unimplemented: Read as ‘0’
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
R/W-0/u
Clears Timer1 gate flip-flop
If T1OSCEN = 0:
External clock from T1CKI pin (on the rising edge)
If T1OSCEN = 1:
Crystal oscillator on T1OSI/T1OSO pins
T1CON: TIMER1 CONTROL REGISTER
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/u
T1CKPS<1:0>
R/W-0/u
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
OSC
T1OSCEN
R/W-0/u
OSC
)
/4)
PIC16(L)F1826/27
OSC
T1SYNC
R/W-0/u
)
U-0
DS41391D-page 185
TMR1ON
R/W-0/u
bit 0

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