SI5110-H-GL Silicon Laboratories Inc, SI5110-H-GL Datasheet - Page 13

• Manufacturer Part Number: SI5110-H-GL
• Description: IC TXRX SONET/SDH LP HS 99LFBGA
• Manufacturer: Silicon Laboratories Inc
• Series: SiPHY®r
• Type: Transceiverr

Specifications of SI5110-H-GL

• Package / Case: 99-LFBGA
• Number Of Drivers/receivers: 1/1
• Protocol: SONET/SDH
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Product: PHY
• Supply Voltage (max): 1.89 V, 3.47 V
• Supply Voltage (min): 1.71 V
• Supply Current: 0.7 A
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 20 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 1300 mW
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

4. Functional Description
The Si5110 transceiver is a low-power, fully-integrated
serializer/deserializer that provides significant margin to
all SONET/SDH jitter specifications. The device
operates from 2.4–2.7 Gbps making it suitable for OC-
48/STM-16
applications that use 255/238 or 255/237 forward error
correction
receive/transmit interface uses a low-power parallel
LVDS interface.
5. Receiver
The receiver within the Si5110 includes a precision
limiting amplifier, a jitter-tolerant clock and data
recovery
Programmable data slicing level and sampling phase
adjustment are provided to support bit-error-rate (BER)
optimization for long haul applications.
5.1. Receiver Differential Input Circuitry
The receiver serial input provides proper termination
and biasing through two resistor dividers internal to the
device. The active circuitry has high-impedance inputs
and provides sufficient gain for the clock and data
recovery unit to recover the serial data. The input bias
levels are optimized for jitter tolerance and input
sensitivity and are typically not dc compatible with
standard I/Os; simply ac couple the data lines as shown
in Figure 10.
5.2. Limiting Amplifier
The Si5110 incorporates a limiting amplifier with
sufficient gain to directly accept the output of
transimpedance amplifiers.
The limiting amplifier provides sufficient gain to fully
saturate with input signals that are greater than 30 mV
peak-to-peak differential. In addition, input signals up to
2 V peak-to-peak differential do not cause any
performance degradation.
5.2.1. Receiver Signal Amplitude Monitoring
The Si5110 limiting amplifier includes circuitry that
monitors the amplitude of the receiver differential input
signal (RXDIN). The RXAMPMON output provides an
analog output signal that is proportional to the input
signal
SLICEMODE
RXAMPMON output is nominally equal to one-half of
the differential peak-to-peak signal amplitude of RXDIN
as shown in Equation 1.
amplitude.
unit
V
RXAMPMON
(FEC)
applications,
is
(CDR),
asserted.
The
≈
coding.
(
V
signal
RXDIN PP
and
The
and
(
1:4
is
)
The
×
voltage
.566
enabled
OC-48/STM-16
demultiplexer.
)
low-speed
on
when
the
Rev. 1.4
The receiver signal amplitude monitoring circuit is also
used in the generation of the loss-of-signal alarm (LOS).
5.2.2. Loss-of-Signal Alarm (LOS)
The Si5110 can be configured to activate a loss-of-
signal alarm output (LOS) when the RXDIN input
amplitude drops below a programmable threshold level.
An appropriate level of hysteresis prevents unnecessary
switching on LOS.
The LOS threshold level is set by applying a dc voltage
to the LOSLVL input. The mapping of the voltage on the
LOSLVL pin to the LOS threshold level depends on the
state of the SLICEMODE input. (The SLICEMODE input
is used to select either Absolute Slice mode or
Proportional Slice mode operation.)
The LOSLVL mapping for Absolute Slice Mode
(SLICEMODE = 0) is given in Figure 4 on page 15. The
linear region of the assert can be approximated by the
following equation:
where V
referred to the RXDIN input, and V
applied to the LOSLVL pin. The linear region of the de-
assert curve can be approximated by the following
equation:
The LOSLVL mapping for Proportional Slice mode
(SLICEMODE = 1) is given in Figure 5 on page 16. The
linear region of the assert can be approximated by the
following equation:
where V
referred to the RXDIN input, and V
applied to the LOSLVL pin.
The linear region of the assert curve can be
approximated be the following equation:
LOS
LOS
is the differential pk-pk LOS threshold
is the differential pk-pk LOS threshold
V
V
V
V
LOS
LOS
LOS
LOS
≈
≈
Equation 1
Equation 2
Equation 3
Equation 4
Equation 5
≈
≈
V
V
V
V
LOSLVL
LOSLVL
LOSLVL
LOSLVL
×
×
×
×
0.958
0.762
0.61
0.72
LOSLVL
LOSLVL
Si5110
is the voltage
is the voltage
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