SI5110-H-GL Silicon Laboratories Inc, SI5110-H-GL Datasheet - Page 30

• Manufacturer Part Number: SI5110-H-GL
• Description: IC TXRX SONET/SDH LP HS 99LFBGA
• Manufacturer: Silicon Laboratories Inc
• Series: SiPHY®r
• Type: Transceiverr

Specifications of SI5110-H-GL

• Package / Case: 99-LFBGA
• Number Of Drivers/receivers: 1/1
• Protocol: SONET/SDH
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Product: PHY
• Supply Voltage (max): 1.89 V, 3.47 V
• Supply Voltage (min): 1.71 V
• Supply Current: 0.7 A
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 20 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 1300 mW
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

S i 5 11 0
30
Number(s)
G10
H10
K10
J10
Pin
G9
E1
H9
K9
H1
K4
H4
K3
F1
J8
J9
J1
TXCLKOUT+,
TXCLKOUT–
TXCLKDSBL
TXMSBSEL
TXDOUT+,
TXDOUT–
TXDIN3+,
TXDIN2+,
TXDIN1+,
TXDIN0+,
TXDIN3–
TXDIN2–
TXDIN1–
TXDIN0–
TXREXT
TXLOL
Name
I/O
O
O
I
I
I
Signal Level
LVTTL
LVTTL
LVTTL
LVDS
CML
Rev. 1.4
High-Speed Transmit Clock Disable.
When this input is high, the output driver for TXCLK-
OUT is disabled. In applications that do not require the
output data clock, the output clock driver should be
disabled to save power.
Note: This input has an internal pulldown.
High-Speed Transmit Clock Output.
The high-speed clock output, TXCLKOUT, is gener-
ated by the PLL in the transmit clock multiplier unit. Its
frequency is nominally 16 times or 32 times the
selected reference source.
Differential Parallel Transmit Data Input.
The 4-bit data word present on these pins is multi-
plexed into a high-speed serial stream and output on
TXDOUT. The bit order for transmit multiplexing is
selected by the TXMSBSEL input. The data on
TXDIN[3:0] is clocked into the device by the rising
edge of TXCLK4IN.
Differential High-Speed Transmit Data Output.
The 4-bit word input on TXDIN[3:0] is multiplexed into
a high-speed serial stream that is output on the TXD-
OUT pins. The bit order for transmit multiplexing is
selected by the TXMSBSEL input. The TXDOUT out-
puts are updated by the rising edge of TXCLKOUT.
Transmit CMU Loss-of-Lock.
The TXLOL output is asserted (low) when the CMU is
not phase locked to the selected reference source or if
REFCLK is not present.
Transmit Data Bus Bit Order Select.
This input determines the order in which data bits
recovered on the TXDIN[3:0] bus are transmitted on
the high-speed serial output TXDOUT.
For TXMSBSEL = 0, data on TXDIN0 is transmitted
first followed by TXDIN1 through TXDIN3.
For TXMSBSEL = 1, TXDIN3 is transmitted first fol-
lowed by TXDIN2 through TXDIN0.
Note: This input has an internal pulldown.
Transmitter External Bias Resistor.
This resistor is used by the transmitter circuitry to
establish bias currents within the device. This pin must
be connected to GND through a 3.09 k Ω ( 1 %) resistor.
Description