SI5110-H-GL Silicon Laboratories Inc, SI5110-H-GL Datasheet - Page 19

• Manufacturer Part Number: SI5110-H-GL
• Description: IC TXRX SONET/SDH LP HS 99LFBGA
• Manufacturer: Silicon Laboratories Inc
• Series: SiPHY®r
• Type: Transceiverr

Specifications of SI5110-H-GL

• Package / Case: 99-LFBGA
• Number Of Drivers/receivers: 1/1
• Protocol: SONET/SDH
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Product: PHY
• Supply Voltage (max): 1.89 V, 3.47 V
• Supply Voltage (min): 1.71 V
• Supply Current: 0.7 A
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 20 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 1300 mW
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Multiplier/Jitter Attenuator IC. Wideband operation
allows the DSPLL to more closely track the precision
reference source, resulting in the best possible jitter
performance.
6.2. Serialization
The Si5110 serialization circuitry is comprised of a FIFO
and a parallel to serial shift register. Low-speed data on
the parallel 4-bit input bus, TXDIN[3:0], is latched into
the FIFO on the rising edge of TXCLK4IN. Data is
clocked out of the FIFO and into the shift register by
TXCLK4OUT. The high-speed serial data stream
TXDOUT is clocked out of the shift register by
TXCLKOUT. The TXCLK4OUT clock is provided as an
output signal to support data word transfers between
the Si5110 and upstream devices using a counter
clocking scheme.
6.2.1. Input FIFO
The Si5110 FIFO decouples the timing of the data
transferred into the device via TXCLK4IN from the data
transferred into the shift register via TXCLK4OUT. The
FIFO is eight parallel words deep and accommodates
any static phase delay that may be introduced between
TXCLK4OUT and TXCLK4IN in counter clocking
schemes. Furthermore, the FIFO accommodates a
bounded phase drift, or wander, between TXCLK4IN
and TXCLK4OUT of up to three parallel data words.
The FIFO circuitry indicates an overflow or underflow
condition by asserting the FIFOERR signal. This output
can be used to re-center the FIFO read/write pointers by
tieing it directly to the FIFORST input.
The FIFORST signal causes re-centering of the FIFO
read/write pointers. The Si5110 also automatically re-
centers the read/write pointers after the device is
powered on, after an external reset via the RESET
input, and each time the DSPLL transitions from an out-
of-lock state to a locked state (when TXLOL transitions
from low to high).
6.2.2. Parallel Input To Serial Output Relationship
The Si5110 provides the capability to select the order in
which the data received on the parallel input bus
TXDIN[3:0] is transmitted serially on the high-speed
serial data output TXDOUT. Data on the parallel bus will
be transmitted MSB first or LSB first depending on the
setting of the TXMSBSEL input. When TXMSBSEL is
set low, TXDIN0 is transmitted first, followed in order by
TXDIN1 through TXDIN3. When TXMSBSEL is set
high, TXDIN3 is transmitted first, followed in order by
TXDIN2 through TXDIN0. This feature can simplify
printed circuit board (PCB) routing in applications where
ICs are mounted on both sides of the PCB.
Rev. 1.4
6.2.3. Transmit Data Squelch
To prevent the transmission of corrupted data into the
network, the Si5110 provides a control pin that can be
used to force the high-speed serial data output
TXDOUT to zero. When the TXSQLCH input is set low,
the TXDOUT signal is forced to a zero state. The
TXSQLCH input is ignored when the device is operating
in Line Loopback mode (LLBK = 0).
6.2.4. Clock Disable
The Si5110 provides a clock disable pin, TXCLKDSBL,
that can be used to disable the high-speed serial data
clock output, TXCLKOUT. When the TXCLKDSBL pin is
asserted, the positive and negative terminals of
CLKOUT are tied internally to 1.5 V through 50 Ω on-
chip resistors.
This feature can be used to reduce power consumption
in applications that do not use the high-speed transmit
data clock.
7. Loop Timed Operation
The Si5110 can be configured to provide SONET/SDH
compliant loop timed operation. When the LPTM input is
set low, the transmit clock and data timing is derived
from the CDR recovered clock output. This is achieved
by dividing down the recovered clock and using it as a
reference source for the transmit CMU. This results in
transmit clock and data signals that are locked to the
timing recovered from the received data path. A narrow-
band loop filter setting is recommended for this mode of
operation.
8. Diagnostic Loopback
The Si5110 provides a Diagnostic Loopback mode that
establishes a loopback path from the serializer output to
the deserializer input. This provides a mechanism for
looping back data input via the low speed transmit
interface TXDIN[3:0] to the low speed receive data
interface RXDOUT[3:0]. This mode is enabled when the
DLBK input is set low.
Note: Setting both DLBK and LLBK low simultaneously is not
9. Line Loopback
The Si5110 provides a Line Loopback mode that
establishes a loopback path from the high-speed
receive input to the high-speed transmit output. This
provides a mechanism for looping back the high-speed
data and clock recovered from RXDIN to the transmit
data output TXDOUT and transmit clock TXCLKOUT.
This mode is enabled when the LLBK input is set low.
Note: Setting both DLBK and LLBK low simultaneously is not
supported.
supported.
Si5110
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