MC145572AACR2 Freescale Semiconductor, MC145572AACR2 Datasheet - Page 84

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MC145572AACR2

Manufacturer Part Number
MC145572AACR2
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC145572AACR2

Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
5–12
5.3.2.1
R/W
CS
D0
D1
D2
D3
D4
D5
D6
D7
PCP NIBBLE REGISTER OPERATION
Data is written to a nibble register using a single PCP write operation. The 8–bit data word must contain
the register address, write bit cleared to 0, and the data to be written as shown in Figure 5–14.
Data is read from a nibble register by first writing the nibble register address with the read indicator
bit set to a 1 to the parallel data port. Next, the parallel data port is read and data from the register
pointed to by the previous write operation appears on bits 0 through 3 of the port. See Figure 5–15.
When NR0 through NR5 are read, software should AND the data read with $0F.
NIBBLE REGISTER WRITE
Figure 5–14. PCP Mode Nibble Register Write and Read Operations
NRA0
NRA1
NRA2
ND0
ND1
ND2
ND3
0
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NRA0
NRA1
NRA2
MC145572
X
X
X
X
1
NIBBLE REGISTER READ
ND0
ND1
ND2
ND3
X
X
X
X
ND x
NRA x Nibble Register Address Bit
X
CS
R/W
Nibble Register Data Bit
Don’t Care
Chip Select
Read/Write Line
KEY
MOTOROLA

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