PIC16LF1826-I/SS Microchip Technology Inc., PIC16LF1826-I/SS Datasheet - Page 256

• Manufacturer Part Number: PIC16LF1826-I/SS
• Description: 3.5 KB Flash, 256 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, n
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16LF1826-I/SS

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SSOP
• Programmable Memory: 3.5K Bytes
• Ram Size: 256 Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16(L)F1826/27
25.5.4
This section describes a standard sequence of events
for the MSSPx module configured as an I
10-bit Addressing mode.
Figure 25-19
description.
This is a step by step process of what must be done by
slave software to accomplish I
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Slave clears SSPxIF.
11. Slave reads the received matching address
12. Slave loads high address into SSPxADD.
13. Master clocks a data byte to the slave and
14. If SEN bit of SSPxCON2 is set, CKP is cleared
15. Slave clears SSPxIF.
16. Slave reads the received byte from SSPxBUF
17. If SEN is set the slave sets CKP to release the
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.
DS41391D-page 256
Note: Updates to the SSPxADD register are not
Note: If the low address does not match, SSPxIF
Bus starts Idle.
Master sends Start condition; S bit of SSPxSTAT
is set; SSPxIF is set if interrupt on Start detect is
enabled.
Master sends matching high address with R/W
bit clear; UA bit of the SSPxSTAT register is set.
Slave sends ACK and SSPxIF is set.
Software clears the SSPxIF bit.
Software reads received address from SSPx-
BUF clearing the BF flag.
Slave loads low address into SSPxADD,
releasing SCLx.
Master sends matching low address byte to the
Slave; UA bit is set.
Slave sends ACK and SSPxIF is set.
from SSPxBUF clearing BF.
clocks out the slaves ACK on the 9th SCLx
pulse; SSPxIF is set.
by hardware and the clock is stretched.
clearing BF.
SCLx.
SLAVE MODE 10-BIT ADDRESS
RECEPTION
allowed until after the ACK sequence.
and UA are still set so that the slave soft-
ware can set SSPxADD back to the high
address. BF is not set because there is no
match. CKP is unaffected.
is used as a visual reference for this
2
C communication.
2
C Slave in
25.5.5
Reception using 10-bit addressing with AHEN or
DHEN set is the same as with 7-bit modes. The only
difference is the need to update the SSPxADD register
using the UA bit. All functionality, specifically when the
CKP bit is cleared and SCLx line is held low are the
same.
slave in 10-bit addressing with AHEN set.
Figure 25-21
transmitter in 10-bit Addressing mode.
Figure 25-20
10-BIT ADDRESSING WITH ADDRESS OR
DATA HOLD
shows a standard waveform for a slave
can be used as a reference of a
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