S29GL512S10DHI020 Spansion Inc., S29GL512S10DHI020 Datasheet - Page 39

• Manufacturer Part Number: S29GL512S10DHI020
• Description: IC 512 MBIT, 3V, 100NS, 64-BALL FBGA, PAGE MODE
• Manufacturer: Spansion Inc.

Specifications of S29GL512S10DHI020

• Lead Free Status / Rohs Status: Supplier Unconfirmed

February 11, 2011 S29GL_128S_01GS_00_01
5.4.2
ECC Status
Notes:
1. Bits 15 thru 8, and 0 are reserved for future use and may display as 0 or 1. These bits should be ignored (masked) when checking status.
2. Bit 7 is 1 when there is no Embedded Algorithm in progress in the device.
3. Bits 6 thru 1 are valid only if Bit 7 is 1.
4. All bits are put in their reset status by cold reset or warm reset.
5. Bits 5, 4, 3, and 1 are cleared to 0 by the Clear Status Register command or Reset command.
6. Upon issuing the Erase Suspend Command, the user must continue to read status until DRB becomes 1.
7. ESSB is cleared to 0 by the Erase Resume Command.
8. ESB reflects success or failure of the most recent erase operation.
9. PSB reflects success or failure of the most recent program operation.
10. During erase suspend, programming to the suspended sector, will cause program failure and set the Program status bit to 1.
11. Upon issuing the Program Suspend Command, the user must continue to read status until DRB becomes 1.
12. PSSB is cleared to 0 by the Program Resume Command.
13. SLSB indicates that a program or erase operation failed because the sector was locked.
14. SLSB reflects the status of the most recent program or erase operation.
The status of ECC in each Page is provided by a single data word.
If a single bit error was corrected when reading the Page, bit 1 = 1 if the error was in the data, bit 2 = 1 if the
error was in the ECC. If the ECC is disabled on the Page due to previous multiple program operations on the
Page, bit 0 = 1. The bits 15 to 3 are reserved and read as a 0.
If the ECC status word = 0, ECC is enabled and no error correction was needed on the Page when read.
Busy Status
Description
Bit Name
Status
Ready
Status
Reset
Bit #
D a t a
Name
Name
Value
Value
Bit
Bit
Bit
Reserved
S h e e t
Invalid
15:8
X
X
RFU
RFU
15
0
7
0
Ready Bit
Device
DRB
( A d v a n c e
7
1
0
1
RFU
RFU
14
0
6
0
Table 5.3 ECC Status Word - Upper 2 Bytes
Table 5.4 ECC Status Word - Lower 2 Bytes
0=No Erase
Suspension
Suspension
1=Erase in
GL-S MirrorBit
Status Bit
Suspend
Invalid
Erase
ESSB
in
6
0
RFU
RFU
Table 5.2 Status Register
13
0
5
0
I n f o r m a t i o n )
1=Erase fail
successful
Status Bit
0=Erase
Invalid
Erase
ESB
®
5
0
Family
RFU
RFU
12
0
4
0
0=Program
1=Program
successful
Status Bit
Program
Invalid
PSB
fail
4
0
RFU
RFU
11
Write Buffer
not aborted
0
3
0
0=Program
1=Program
command
Status Bit
WBASB
aborted
Write to
Invalid
during
Buffer
Abort
3
0
1= Single Bit
0 =No Error
Corrected
Corrected
Corrected
Single Bit
ECC Bits
Error
Error
RFU
suspension
1=Program
suspension
Program in
10
Status Bit
Suspend
0
Program
2
Invalid
PSSB
0=No
in
2
0
1= Single Bit
0 =No Error
Corrected
Corrected
Corrected
Single Bit
Data Bits
Sector Lock
locked error
not locked
Status Bit
Error
Error
0=Sector
operation
1=Sector
RFU
Invalid
during
SLSB
9
0
1
1
0
Disabled
Disabled
Reserved
Enabled
0=ECC
1=ECC
Invalid
ECC
RFU
8
0
0
X
0
0
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