MM912H634CM1AE Freescale Semiconductor, MM912H634CM1AE Datasheet - Page 109

• Manufacturer Part Number: MM912H634CM1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.16.2.5
This register has one read-only status flag.
Note:
Freescale Semiconductor
Offset
96.
Reset
W
R
Field
IDLE
OR
NF
FE
PF
(96)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
4
3
2
1
0
0x45
LBKDIF
Idle Line Flag — IDLE is set when the SCI receive line becomes idle for a full character time after a period of activity. When
ILT = 0, the receiver starts counting idle bit times after the start bit. So if the receive character is all 1s, these bit times and the
stop bit time count toward the full character time of logic high (10 or 11 bit times depending on the M control bit) needed for the
receiver to detect an idle line. When ILT = 1, the receiver doesn’t start counting idle bit times until after the stop bit. So the stop
bit and any logic high bit times at the end of the previous character do not count toward the full character time of logic high
needed for the receiver to detect an idle line.
To clear IDLE, read SCIS1 with IDLE = 1 and then read the SCI data register (SCID). After IDLE has been cleared, it cannot
become set again until after a new character has been received and RDRF has been set. IDLE will get set only once even if
the receive line remains idle for an extended period.
Receiver Overrun Flag — OR is set when a new serial character is ready to be transferred to the receive data register (buffer),
but the previously received character has not been read from SCID yet. In this case, the new character (and all associated
error information) is lost because there is no room to move it into SCID. To clear OR, read SCIS1 with OR = 1 and then read
the SCI data register (SCID).
Noise Flag — The advanced sampling technique used in the receiver takes seven samples during the start bit and three
samples in each data bit and the stop bit. If any of these samples disagrees with the rest of the samples within any bit time in
the frame, the flag NF will be set at the same time as the flag RDRF gets set for the character. To clear NF, read SCIS1 and
then read the SCI data register (SCID).
Framing Error Flag — FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop bit was expected.
This suggests the receiver was not properly aligned to a character frame. To clear FE, read SCIS1 with FE = 1 and then read
the SCI data register (SCID).
Parity Error Flag — PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in the received
character does not agree with the expected parity value. To clear PF, read SCIS1 and then read the SCI data register (SCID).
SCI Status Register 2 (SCIS2)
7
0
0
1
0
1
0
1
0
1
0
1
No idle line detected.
Idle line was detected.
No overrun.
Receive overrun (new SCI data lost).
No noise detected.
Noise detected in the received character in SCID.
No framing error detected. This does not guarantee the framing is correct.
Framing error.
No parity error.
Parity error.
RXEDGIF
6
0
Table 143. SCIS1 Field Descriptions (continued)
Table 144. SCI Status Register 2 (SCIS2)
MM912_634 Advance Information, Rev. 4.0
5
0
0
RXINV(97)
4
0
Description
RWUID
3
0
Serial Communication Interface (S08SCIV4)
BRK13
2
0
LBKDE
1
0
Access: User read/write
RAF
0
0
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