PIC24EP64MC204-E/PT Microchip Technology, PIC24EP64MC204-E/PT Datasheet - Page 235

• Manufacturer Part Number: PIC24EP64MC204-E/PT
• Description: 16 Bit MCU, 64KB Flash, 8KB RAM, 60 MHz, 44 Pin, MCPWM,QEI, 3 OpAmp, 4 Comp, PTG
• Manufacturer: Microchip Technology

REGISTER 16-7:
 2011-2012 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Note 1:
FLTSTAT
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
HS/HC-0
R/W-0
2:
3:
4:
5:
DTC<1:0>
(1)
Software must clear the interrupt status here and in the corresponding IFS bit in the interrupt controller.
These bits should not be changed after the PWM is enabled (PTEN = 1).
DTC<1:0> = 11 for DTCP to be effective; otherwise, DTCP is ignored.
The Independent Time Base (ITB = 1) mode must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
To operate in External Period Reset mode, the ITB bit must be ‘1’ and the CLMOD bit in the FCLCONx
register must be ‘0’.
FLTSTAT: Fault Interrupt Status bit
1 = Fault interrupt is pending
0 = No Fault interrupt is pending
This bit is cleared by setting FLTIEN = 0.
CLSTAT: Current-Limit Interrupt Status bit
1 = Current-limit interrupt is pending
0 = No current-limit interrupt is pending
This bit is cleared by setting CLIEN = 0.
TRGSTAT: Trigger Interrupt Status bit
1 = Trigger interrupt is pending
0 = No trigger interrupt is pending
This bit is cleared by setting TRGIEN = 0.
FLTIEN: Fault Interrupt Enable bit
1 = Fault interrupt is enabled
0 = Fault interrupt is disabled and FLTSTAT bit is cleared
CLIEN: Current-Limit Interrupt Enable bit
1 = Current-limit interrupt enabled
0 = Current-limit interrupt disabled and CLSTAT bit is cleared
TRGIEN: Trigger Interrupt Enable bit
1 = A trigger event generates an interrupt request
0 = Trigger event interrupts are disabled and TRGSTAT bit is cleared
ITB: Independent Time Base Mode bit
1 = PHASEx register provides time base period for this PWM generator
0 = PTPER register provides timing for this PWM generator
MDCS: Master Duty Cycle Register Select bit
1 = MDC register provides duty cycle information for this PWM generator
0 = PDCx register provides duty cycle information for this PWM generator
CLSTAT
HS/HC-0
R/W-0
PWMCONx: PWM CONTROL REGISTER
(1)
W = Writable bit
HC = Cleared in Hardware HS = Set in Hardware
‘1’ = Bit is set
TRGSTAT
HS/HC-0
DTCP
R/W-0
(3)
FLTIEN
R/W-0
U-0
—
(1)
(2)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
CLIEN
R/W-0
R/W-0
MTBS
CAM
TRGIEN
R/W-0
R/W-0
(2,4)
x = Bit is unknown
XPRES
R/W-0
R/W-0
ITB
(2)
(5)
DS70657F-page 235
MDCS
R/W-0
R/W-0
IUE
(2)
(2)
bit 8
bit 0