PIC24EP64MC204-E/PT Microchip Technology, PIC24EP64MC204-E/PT Datasheet - Page 329

• Manufacturer Part Number: PIC24EP64MC204-E/PT
• Description: 16 Bit MCU, 64KB Flash, 8KB RAM, 60 MHz, 44 Pin, MCPWM,QEI, 3 OpAmp, 4 Comp, PTG
• Manufacturer: Microchip Technology

REGISTER 23-6:
 2011-2012 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-13
bit 12-8
bit 7
bit 6-5
Note 1:
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
CH0NB
CH0NA
R/W-0
R/W-0
2:
3:
AN0 through AN7 are repurposed when comparator and op amp functionality is enabled. See
to determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2,
and 3.
If the Op amp is selected (OPMODE bit (CMxCON<10>) = 1), the OAx input is used; otherwise, the ANx
input is used.
See the
CH0NB: Channel 0 Negative Input Select for Sample MUXB bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is V
Unimplemented: Read as ‘0’
CH0SB<4:0>: Channel 0 Positive Input Select for Sample MUXB bits
11111 = Open; use this selection with CTMU capacitive and time measurement
11110 = Channel 0 positive input is connected to CTMU temperature measurement diode
11101 = Reserved
11100 = Reserved
11011 = Reserved
11010 = Channel 0 positive input is output of OA3/AN6
11001 = Channel 0 positive input is output of OA2/AN0
11000 = Channel 0 positive input is output of OA1/AN3
10111 = Reserved
•
•
•
10000 = Reserved
01111 = Channel 0 positive input is AN15
01110 = Channel 0 positive input is AN14
01101 = Channel 0 positive input is AN13
•
•
•
00010 = Channel 0 positive input is AN2
00001 = Channel 0 positive input is AN1
00000 = Channel 0 positive input is AN0
CH0NA: Channel 0 Negative Input Select for Sample MUXA bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is V
Unimplemented: Read as ‘0’
“Pin Diagrams”
U-0
U-0
—
—
AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER
(CTMU TEMP)
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
section for the available analog channels for each device.
R/W-0
R/W-0
REFL
REFL
(1)
(1)
(3)
(3)
(3)
(3)
(3)
(3)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
R/W-0
(2)
(2)
(2)
CH0SB<4:0>
CH0SA<4:0>
R/W-0
R/W-0
(1)
x = Bit is unknown
R/W-0
R/W-0
DS70657F-page 329
Figure 23-1
R/W-0
R/W-0
bit 8
bit 0