PIC24EP64MC204-E/PT Microchip Technology, PIC24EP64MC204-E/PT Datasheet - Page 281

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PIC24EP64MC204-E/PT

Manufacturer Part Number
PIC24EP64MC204-E/PT
Description
16 Bit MCU, 64KB Flash, 8KB RAM, 60 MHz, 44 Pin, MCPWM,QEI, 3 OpAmp, 4 Comp, PTG
Manufacturer
Microchip Technology
Datasheet

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20.0
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X, and PIC24EPXXXGP/MC20X family of devices
contain two UART modules.
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules
available
dsPIC33EPXXXMC20X/50X, and PIC24EPXXXGP/
MC20X device family. The UART is a full-duplex
asynchronous system that can communicate with
peripheral devices, such as personal computers, LIN,
RS-232 and RS-485 interfaces. The module also
supports a hardware flow control option with the UxCTS
and UxRTS pins and also includes an IrDA
and decoder.
FIGURE 20-1:
 2011-2012 Microchip Technology Inc.
Note:
Note 1: This data sheet summarizes the features
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
2: Some registers and associated bits
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
Hardware flow control using UxRTS and
UxCTS is not available on all pin count
devices. See the
for availability.
of
dsPIC33EPXXXMC20X/50X,
PIC24EPXXXGP/MC20X
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 17. “UART”
(DS70582) of the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
in
the
the
UART SIMPLIFIED BLOCK DIAGRAM
“Pin Diagrams”
dsPIC33EPXXXGP50X,
dsPIC33EPXXXGP50X,
Hardware Flow Control
Baud Rate Generator
UART Transmitter
UART Receiver
IrDA
families
®
®
encoder
section
and
of
in
The primary features of the UART module are:
• Full-Duplex, 8- or 9-bit Data Transmission through
• Even, Odd or No Parity Options (for 8-bit data)
• One or two stop bits
• Hardware flow control option with UxCTS and
• Fully integrated Baud Rate Generator with 16-bit
• Baud rates ranging from 4.375 Mbps to 67 bps at
• Baud rates ranging from 17.5 Mbps to 267 bps at
• 4-deep First-In First-Out (FIFO) Transmit Data
• 4-deep FIFO Receive Data buffer
• Parity, framing and buffer overrun error detection
• Support for 9-bit mode with Address Detect
• Transmit and Receive interrupts
• A separate interrupt for all UART error conditions
• Loopback mode for diagnostic support
• Support for Sync and Break characters
• Support for automatic baud rate detection
• IrDA
• 16x baud clock output for IrDA
A simplified block diagram of the UART module is
shown in
these key hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
the UxTX and UxRX pins
UxRTS pins
prescaler
16x mode at 70 MIPS
4x mode at 70 MIPS
buffer
(9th bit = 1)
®
encoder and decoder logic
Figure
20-1. The UART module consists of
UxTX
UxRTS/BCLKx
UxCTS
UxRX
®
support
DS70657F-page 281

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