5V49EE703NDGI8 IDT, Integrated Device Technology Inc, 5V49EE703NDGI8 Datasheet - Page 19

• Manufacturer Part Number: 5V49EE703NDGI8
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Programmable PLL Clock Synthesizerr

Specifications of 5V49EE703NDGI8

• Number Of Elements: 4
• Pll Input Freq (min): 1MHz
• Pll Input Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFQFPN EP
• Output Frequency Range: 0.001 to 200MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Pin Count: 28
• Lead Free Status / Rohs Status: Compliant

AC Timing Electrical Characteristics
(Spread Spectrum Generation = OFF)
1.Practical lower frequency is determined by loop filter settings.
2.A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.
3.Jitter measured with clock outputs of 27 MHz, 48 MHz, 24.576 MHz, 74.25 MHz and 25 MHz.
4.Includes loading the configuration bits from EEPROM to PLL registers. It does not include EEPROM programming/write time.
5.Actual PLL lock time depends on the loop configuration.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
Symbol
IDT5V49EE703
EEPROM PROGRAMMABLE CLOCK GENERATOR
1 / t1
f
f
f
f
t4
t7
t8
VCO
PFD
IN
BW
t2
t3
t5
t6
2
4
5
1
Input Frequency
Output Frequency
VCO Frequency
PFD Frequency
Loop Bandwidth
Input Duty Cycle
Output Duty Cycle
Slew Rate, SLEW[1:0] = 00
Slew Rate, SLEW[1:0] = 01
Slew Rate, SLEW[1:0] = 10
Slew Rate, SLEW[1:0] = 11
Clock Jitter
Output Skew
Lock Time
Lock Time
Parameter
Input frequency limit (CLKIN)
Input frequency limit (XIN/REF)
VCO operating frequency range
PFD operating frequency range
Based on loop filter resistor and capacitor
values
Duty Cycle for input
Measured at V
Reference output
Measured at V
Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of V
(Output Load = 15 pF)
Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of V
(Output Load = 15 pF)
Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of V
(Output Load = 15 pF)
Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of V
(Output Load = 15 pF)
Peak-to-peak period jitter, 1PLL, multiple
output frequencies switching
Peak-to-peak period jitter, all 4 PLLs on
Skew between output to output on the same
bank
PLL lock time from power-up
PLL lock time from shutdown mode
Test Conditions
DD
DD
19
/2, all outputs except
/2, Reference output
DD
DD
DD
DD
3
0.001
Min.
0.5
0.01
100
40
45
40
1
8
1
IDT5V49EE703
CLOCK SYNTHESIZER
Typ.
2.75
1.25
200
3.5
80
10
2
Max.
1200
200
100
200
100
100
270
10
60
55
60
75
20
2
REV F 022310
Units
MHz
MHz
MHz
MHz
MHz
MHz
V/ns
ms
ms
ps
ps
ps
%
%
%