5V49EE703NDGI8 IDT, Integrated Device Technology Inc, 5V49EE703NDGI8 Datasheet - Page 9

• Manufacturer Part Number: 5V49EE703NDGI8
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Programmable PLL Clock Synthesizerr

Specifications of 5V49EE703NDGI8

• Number Of Elements: 4
• Pll Input Freq (min): 1MHz
• Pll Input Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFQFPN EP
• Output Frequency Range: 0.001 to 200MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Pin Count: 28
• Lead Free Status / Rohs Status: Compliant

Profile:
Waveform starts with SS_OFFSET, SS_OFFSET + SD
SS_OFFSET + SD
Spread Spectrum Using Sinusoidal Profile
Example
F
spread of ±2%. Find the necessary spread spectrum
register settings.
Since the spread is center, the SS_OFFSET can be set to
'0'. Solve for the nominal M value; keep in mind that the
nominal M should be chosen to maximize
the VCO. Start with D = 1, using Eq.6 and Eq.7.
M
Using Eq.4, we arbitrarily choose N = 22, A = 3. Now that we
have the nominal M value, we can determine TSSC and
NSSC by using Eq.8.
Nssc * Tssc = 25MHz / (33KHz * 4) = 190
However, using Eq. 2 and Eq.3, we find that the closest
value is when TSSC = 14 and NSSC = 6. Keep in mind to
maximize the number of samples used
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
IN
NOM
IDT5V49EE703
EEPROM PROGRAMMABLE CLOCK GENERATOR
= 25MHz, F
= 1200MHz / 25MHz = 48
OUT
J+1
= 100MHz, Fssc = 33KHz with center
, etc.
J
,
9
to enhance the profile of the spread spectrum waveform.
Tssc = 14 + 2 = 16
Nssc = 6 * 2 = 12
Nssc * Tssc = 192
Use Eq.10 to determine the value of the
sigma-delta-encoded samples.
±2% = (Σ∆ * 100)/(64 * 48)
Σ∆ = 61.4
Either round up or down to the nearest integer value.
Therefore, we end up with 61 or 62 for sigma-delta-encoded
samples. Since the sigma-delta-encoded samples must not
exceed 63 with SS_OFFSET set to '0', 61 or 62 is well within
the limits. It is the discretion of the user to define the shape
of the profile that is better suited for the intended application.
Using Eq. 9 again, the actual spread for the
sigma-delta-encoded samples of 56 and 57 are ±1.99% and
±2.02%, respectively.
Use Eq.10 to determine if the X2 bit needs to be set;
Amplitude = 48 * (1.99 or 2.02) / 100/2 = 0.48 < 1
Therefore, the X2 = '0 '. The dither bit is left to the discretion
of the user.
The example above was of a center spread using spread
spectrum. For down spread, the nominal M value can be set
one integer value lower to 47.
Note that the IDT5V49EE703 should not be programmed
with TSSC > '0', SS_OFFSET = '0', and SD = '0' in order to
prevent an unstable state in the modulator.
The PLL loop bandwidth must be at least 10x the
modulation frequency along with higher damping (larger
ωuz) to prevent the spread spectrum from being filtered and
reduce extraneous noise. Refer to the LOOP FILTER
section for more detail on ωuz. The A[3:0] must be used for
spread spectrum, even if the total multiplier value is an even
integer.
IDT5V49EE703
CLOCK SYNTHESIZER
REV F 022310