TJA1041AT/N,112 NXP Semiconductors, TJA1041AT/N,112 Datasheet - Page 8

• Manufacturer Part Number: TJA1041AT/N,112
• Description: IC TXRX CAN 14BIT 27V SOT108-1
• Manufacturer: NXP Semiconductors
• Type: Transceiverr

Specifications of TJA1041AT/N,112

• Number Of Drivers/receivers: 1/1
• Protocol: CAN
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935277288112; TJA1041AT/N; TJA1041AT/N

NXP Semiconductors
TJA1041A_4
Product data sheet
7.2.1 UV
7.2.2 UV
7.2.3 Pwon flag
7.2.4 Wake-up flag
Table 5.
[1]
[2]
UV
on pin V
drops below V
will enter Sleep mode to save power and not disturb the bus. In Sleep mode the voltage
regulators connected to pin INH are disabled, avoiding the extra power consumption in
case of a short circuit condition. After a waiting time (fixed by the same timers used for
setting UV
timers, allowing the voltage regulators to be reactivated at least until UV
UV
pin V
Standby mode to save power and not disturb the bus. UV
on pin V
determined by the logic state of pins STB and EN.
Pwon is the V
recovered after it dropped below V
disconnected from the battery. By setting the pwon flag, the UV
cleared and the transceiver cannot enter Sleep mode. This ensures that any voltage
regulator connected to pin INH is activated when the node is reconnected to the battery. In
Pwon/Listen-only mode the pwon flag can be made available on pin ERR. The flag is
cleared when the transceiver enters Normal mode.
The wake-up flag is set when the transceiver detects a local or a remote wake-up request.
A local wake-up request is detected when a logic state change on pin WAKE remains
stable for at least t
states of at least t
least t
mode or Sleep mode. Setting of the flag is blocked during the UV
setting the wake-up flag, the UV
Internal
flag
wake-up
source
bus failure
local failure
NOM
BAT
NOM
BAT
Pin ERR is an active-LOW output, so a LOW-level indicates a set flag and a HIGH-level indicates a cleared
flag. Allow pin ERR to stabilize for at least 8 s after changing operating modes.
Allow for a TXD dominant time of at least 4 s per dominant-recessive cycle.
BAT
BUSrec
is the V
is the V
flag
CC
BAT
flag
drops below V
NOM
Accessing internal flags via pin ERR
drops below V
). The wake-up flag can only be set in Standby mode, Go-to-sleep command
has recovered. The transceiver will then return to the operating mode
Flag is available on pin ERR
in Normal mode (before the fourth
dominant to recessive edge on pin TXD
in Normal mode (after the fourth dominant
to recessive edge on pin TXD
in Pwon/Listen-only mode (coming from
Normal mode)
BAT
I/O(sleep)
) any wake-up request or setting of the pwon flag will clear UV
BAT
CC
power-on flag. This flag is set when the voltage on pin V
BUSdom
undervoltage detection flag. The flag is set when the voltage on
and V
wake
for longer than t
. A remote wake-up request is detected after two bus dominant
BAT(stb)
Rev. 04 — 29 July 2008
I/O
(with each dominant state followed by a recessive state of at
CC(sleep)
undervoltage detection flag. The flag is set when the voltage
. When UV
NOM
for longer than t
BAT(pwon)
flag and timers are cleared. The wake-up flag is
UV(VI/O)
[2]
[1]
BAT
)
, particularly after the transceiver was
is set, the transceiver will try to enter
. When the UV
…continued
[2]
UV(VCC)
)
Flag is cleared
on leaving Normal mode, or by setting
the pwon flag
on reentering Normal mode
on entering Normal mode or when RXD
is dominant while TXD is recessive
(provided that all local failures are
resolved)
BAT
or when the voltage on pin V
High-speed CAN transceiver
NOM
is cleared when the voltage
NOM
flag is set, the transceiver
NOM
TJA1041A
flag and timers are
flag waiting time. By
© NXP B.V. 2008. All rights reserved.
NOM
BAT
NOM
is set again.
has
and the
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I/O