DS90CF383AMTD National Semiconductor, DS90CF383AMTD Datasheet
DS90CF383AMTD
Specifications of DS90CF383AMTD
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DS90CF383AMTD Summary of contents
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... This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. Block Diagram Order Number DS90C383AMTD or DS90CF383AMTD TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2003 National Semiconductor Corporation ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Duration Junction Temperature Storage Temperature Lead Temperature (Soldering, 4 sec) ...
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Recommended Transmitter Input Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol TCIT TxCLK IN Transition Time (Figure 5 ) TCIP TxCLK IN Period (Figure 6 ) TCIH TxCLK IN High Time (Figure 6 ) TCIL TxCLK ...
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AC Timing Diagrams FIGURE 2. “16 Grayscale” Test Pattern (Notes 10) Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 8: The 16 grayscale test pattern ...
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AC Timing Diagrams (Continued) FIGURE 3. DS90C383A/DS90CF383A (Transmitter) LVDS Output Load FIGURE 4. DS90C383A/DS90CF383A (Transmitter) LVDS Transition Times FIGURE 5. DS90C383A/DS90CF383A (Transmitter) Input Clock Transition Time FIGURE 6. DS90C383A/DS90CF383A (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe) FIGURE 7. DS90C383A/DS90CF383A ...
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AC Timing Diagrams FIGURE 8. DS90C383A/DS90CF383A (Transmitter) Phase Lock Loop Set Time FIGURE 9. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs www.national.com (Continued) FIGURE 10. Transmitter Power Down Delay 6 10010014 10010017 10010018 ...
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AC Timing Diagrams (Continued) FIGURE 11. Transmitter LVDS Output Pulse Position Measurement FIGURE 12. TJCC Test Setup 7 10010026 10010027 www.national.com ...
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AC Timing Diagrams FIGURE 13. Timing Diagram of the Input cycle-to-cycle clock jitter DS90C383A Pin Description—FPD Link Transmitter Pin Name I/O No. TxIN I 28 TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines ...
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DS90CF383A Pin Description—FPD Link Transmitter Pin Name I/O No. TxIN I 28 TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE, FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable). ...
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Pin Diagram DS90C383A www.national.com 10010023 Typical Application TABLE 1. Programmable Transmitter (DS90C383A) Pin Condition Strobe Status R_FB R_FB = V Rising edge strobe CC R_FB R_FB = GND or NC Falling edge strobe 10 DS90CF383A 10010024 10010003 ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise noted Order Number DS90C383AMTD, DS90CF383AMTD NS Package Number MTD56 2 ...