MC145574APB Freescale Semiconductor, MC145574APB Datasheet - Page 94

• Manufacturer Part Number: MC145574APB
• Description: IC TRANSCEIVER ISDN 32-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC145574APB

• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Not Compliant

10–4
10.8
OR6
OR6(7) — Control Register, TSA B1 Enable
This bit is used to enable the B1 channel in IDL2 timeslot mode. The B1 timeslot is defined through
the OR0 and OR3 registers. Whenever any channel (B1, B2, or D) is enabled for timeslot mode, all
channels enter timeslot mode. If in timeslot mode and TSA B1 enable is a 0, then the B1 channel
is not present on D out , and the transmit data on the S/T interface is forced to all 1s and D out is high
impedance.
OR6(6) — Control Register, TSA B2 Enable
This bit is used to enable the B2 channel in IDL2 timeslot mode. The B2 timeslot is defined through
OR1 and OR4 registers. Whenever any channel (B1, B2, or D) is enabled for timeslot mode, all chan-
nels enter timeslot mode. If in timeslot mode and TSA B2 enable is a 0, then the B2 channel is not
present on D out , and the transmit data on the S/T interface is forced to all 1s and D out is high impedance.
OR6(5) — Control Register, TSA D Channel Enable
This bit is used to enable the D channel in IDL2 timeslot mode. The D timeslot is defined through
the OR2 and OR5 registers. Whenever any channel (B1, B2, or D) is enabled for timeslot mode, all
channels enter timeslot mode. If in timeslot mode and TSA D enable is a 0, then the D channel is
not present on D out , and the transmit data on the S/T interface is forced to all 1s and D out is high
impedance.
OR6(3) — Control Register, D out Open Drain
When operating in NT Terminal mode, this bit configures the D out pin as an open drain when set to
a 1. When this bit is set to a 0, the D out pin goes high impedance between B and D channels.
OR6(2) — Control Register, GCI Indirect Mode Enable
When the device is initialized, this bit is a logic 0, the inactive state; i.e., normal IDL2 mode. When
set to a logic 1, the IDL2 port is reconfigured to behave like a GCI frame. This is called GCI indirect
mode. When GCI indirect mode has been enabled, the GCI timeslot can be selected through the S(2:0)
bits in OR5.
OR6(1:0) — Control Register, CLK(1:0)
In GCI indirect mode, these two bits control the output clock frequency of GCI DCL. CLK(1:0)=0H
is the initialized state.
OR6
TSA B1
Enable
(7)
TSA B2
Enable
(6)
Table 10–4. S(2:0) GCI Timeslot
Channel
TSA D
Enable
MC145574
CLK1
(5)
0
0
1
1
Assignment
CLK0
0
1
0
1
(4)
Open Drain
2.048 MHz
2.048 MHz
1.536 MHz
GCI DCL
512 kHz
D out
(3)
Indirect
Enable
Mode
GCI
(2)
CLK1
(1)
MOTOROLA
CLK0
(0)