SAB-C161PI-LF 3V CA Infineon Technologies, SAB-C161PI-LF 3V CA Datasheet - Page 68

• Manufacturer Part Number: SAB-C161PI-LF 3V CA
• Description: Microcontrollers (MCU) 16BIT SNGL CHIP 3.3V 20MHz ROM less
• Manufacturer: Infineon Technologies

Specifications of SAB-C161PI-LF 3V CA

• Data Bus Width: 16 bit
• Program Memory Type: ROMLess
• Data Ram Size: 3 KB
• Interface Type: ASC, I2C, SSC
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 5
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 4 Channel
• Packages: PG-TQFP-100
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 3.0 KByte
• A / D Input Lines (incl. Fadc): 4
• Program Memory: 0.0 KByte
• Lead Free Status / Rohs Status: Details
• Other names: B161PILF3VCAXT

Data Sheet
Demultiplexed Bus (Standard Supply Voltage Range) (continued)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
Parameter
Address hold after
RdCS, WrCS
Data hold after WrCS
1) RW-delay and
2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
Therefore address changes before the end of RD have no impact on read cycles.
specified together with the address and signal BHE (see figures below).
A
refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
Symbol
55
57
A
+
CC -6 +
CC 6 +
C
+
F
Max. CPU Clock
(80 ns at 25 MHz CPU clock without waitstates)
min.
= 25 MHz
F
F
66
–
–
max.
1 / 2TCL = 1 to 25 MHz
-6 +
TCL - 14 +
F
Variable CPU Clock
min.
F
–
–
max.
&3,
1999-07
Unit
ns
ns