Z8622912PSG Zilog, Z8622912PSG Datasheet - Page 27

• Manufacturer Part Number: Z8622912PSG
• Description: IC CCD W/2ND I2C ADD 18-DIP
• Manufacturer: Zilog
• Type: Video Decoderr

Specifications of Z8622912PSG

• Applications: Set-Top Boxes, TV
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Processor Series: Z8622x
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: CGROM
• Program Memory Size: 3.7 B
• Maximum Clock Frequency: 12 MHz
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Lead Free Status / Rohs Status: Details

ZiLOG
Read And Write Commands
Read Selects.
(RDS1 and RDS2) in the Z86229. Each command is one
byte in size and indicates that a read should take place.
RDS1 specifies that one byte is read from the Z86229; like-
wise, RDS2 indicates that two bytes are read.
RDS1 = 40h–47h.
initiate a one-byte read sequence. This action is performed
by moving the contents of the register identified by the ad-
dress field (AD00:02) of the command to the output register.
Addresses 0h–7h are valid in the RDS1 command field
AD00:02.
RDS2 = 60h–66h.
used to initiate a two-byte read sequence. This action is per-
formed by moving the contents of the two consecutive reg-
isters, starting with the one identified by the address portion
of the command (AD00:AD02), to the output registers, set-
ting the RD2 bit in the SS register. Only Addresses 0h–6h
are valid in the RDS2 command field AD00:02.
Note: *Changing the ON/OFF state of the 16-Second Erase
Timer has no affect on the current display mode in operation.
Bit
Bit
CM7
W
W
7
0
0
Table 14. XDS Display Commands*
Figure 14. RSD2–Read Two Bytes
CM6
Figure 13. RDS1–Read One Byte
W
1
W
1
6
There are two Read Select commands
CM5
RDS1 is a one-byte command used to
RDS2 is a one-byte command which is
(RDS1 = 40h–47h)
W
(RDS2 = 60h–66h)
5
1
0
W
CM4
4
0
W
0
W
AD03
CM3 CM2
W
3
W
0
AD02 AD01 AD00
AD02 AD01 AD00
W
2
W
CM1
1
W
W
CM0
0
W
W
Note:
Reading Data From The Z86229
READ1 = F8h.
READ2 = F9h.
The READx commands do not affect the status of the RDY
bit in the Serial Status (SS) register, and can be executed
independent of the RDY status.
In both serial communications modes, the DAV bit in the
SS register indicates when the data is available. When the
RD2 bit is Low, the DAV is cleared on the rising edge of
SCK at the LSB of the first data byte. When the RD2 bit is
High, the DAV is cleared on the rising edge of SCK at the
LSB of the second data byte. The RD2 bit is only valid if
the DAV is High.
Reading in the I
Slave Address byte. The first byte after the Slave Address
byte is SS followed by the data in output buffers (A and B,
respectively). If the instruction being executed is a one-byte
read, then buffer A contains the read data and buffer B con-
tains all ones.
Writing to the Z86229
WRxx = C0h–DFh
Bit
Bit
W
7
1
For XDS data recovery, when the XDS Filter Register
(see Internal Register section) is enabled for the packets,
the Z86229 automatically establishes the two-byte recov-
ery mode, moving the recovered data bytes to the output
register.
W
1
7
Figure 16. WRxx–Write Register xx
Figure 15. READx–Read x Bytes
W
1
W
6
1
6
This command reads one byte in the SPI mode.
This command reads two bytes in the SPI mode.
2
C mode is selected by the R/NW bit in the
(READ1/2 = F8h/F9h)
W
(WRx = C0h–DFh)
5
5
W
1
0
4
W
4
1
0
W
W
1
W
3
3
0
AD02 AD01 AD00
0
2
W
2
W
1
0
1
W
W
RD2
W
W
0
0