Z8622912PSG Zilog, Z8622912PSG Datasheet - Page 32

• Manufacturer Part Number: Z8622912PSG
• Description: IC CCD W/2ND I2C ADD 18-DIP
• Manufacturer: Zilog
• Type: Video Decoderr

Specifications of Z8622912PSG

• Applications: Set-Top Boxes, TV
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Processor Series: Z8622x
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: CGROM
• Program Memory Size: 3.7 B
• Maximum Clock Frequency: 12 MHz
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Lead Free Status / Rohs Status: Details

+ 0 6 ' 4 0 # . 4 ' ) + 5 6 ' 4 5
D
output through the Serial Control port when XDS recovery
has been enabled.
D
ters, tabulated below, to be used in filtering the XDS data
when XDS recovery has been enabled.
Interrupt Request Register Address = 06h
D0–res.
D
ed. This bit clears in each field a few lines after row 15.
D
currently at the end of a field. This bit clears in each field
a few lines after row 15.
Notes:
Bit
4
5
Figure 25. Interrupt Request Register (Address = 06h)
1
2
–PUBL.
–D
–DLE.
–EOF.
1. Setting this register to 00h turns XDS data recovery off.
2. The Time Information includes the Time of Day (TOD) and
3. The VCR Information selects TOD, LTZ, Net ID, Local Call
dTXT dCAP
R/W
7
Setting bits D
classes selected, as qualified by the secondary filter (bits
D
data will be output, even the reserved and undefined
classes.
Local Time Zone (LTZ) packets.
Letters, Impulse Capture, Tape Delay, Composite 2, and
Out-of-Band Channel Number packets for recovery.
D
–s
5
7
–D
Table 17. XDS Secondary Filter Settings
Reserved.
0
Active High, indicating that the data line has end-
Active High, indicating that the video signal is
–s
7
This bit selects Public Service Class packets for
R/W
). If bits D
2
D
.
6
This bit selects a set of secondary parame-
dXDS

0
R/W

D
through D
5
0
–D
4
dSCH
R/W
D
are all set to “1”, all classes of XDS
4
4
% Q P V K P W G F
enables XDS recovery for the
dLOK
R/W
D
3
EOF
D
R
2
DLE
D
R
1
1
D
res
R
0
D
LOCK signal has changed. The SS register must be read to
determine the current state.
D
channel activity has occurred. The Line 21 Activity register
must be read in order to determine if the selected data chan-
nel is active.
D
tivity has occurred. The Line 21 Activity register must be
read to determine if XDS data is active.
D
tivity has occurred. The Line 21 Activity register must be
read to determine if XDS data is active.
D
tion data channel activity has occurred. The Caption Activ-
ity Register (Address 08h) must be read to determine ex-
actly which caption channels are now active.
D
data channel activity has occurred. The Caption Activity
Register (Address 08h) must be read to determine exactly
which text channels are now active.
Note:
Interrupt Mask Register Address = 07h
This register identifies which activities in the Interrupt Re-
quest Register are used to cause an interrupt. Setting a bit
to a 1 enables the interrupt when the corresponding event
becomes active. Setting all bits of this register to zero dis-
ables interrupts. The Caption Activity Register Address =
08h.
Bit
3
4
5
5
6
7
–dLOK.
–dSCH.
–dXDS.
–dXDS.
–dCAP.
–dTXT.
Figure 26. Interrupt Mask Register Address = 07h
dTXT
R/W
D
Except as noted for the case of D1 and D2 above, the mas-
ter device must write a 1 to the appropriate bit in the In-
terrupt Request Register to clear the Interrupt. Writing a
1 to any valid bit position, the Interrupt Request Register
is equivalent to CLEARing a interrupt request on that bit.
7
Active High, indicating that a change in a Text
Active High, indicating that the state of the
Active High, indicating that a change in XDS ac-
Active High, indicating that a change in XDS ac-
Active High, indicating that a change in a cap-
dCAP
Active High, indicating that a change in selected
R/W
D
6
dXDS
R/W
D
5
dSCH
R/W
D
4
dLOK
R/W
D
3
EOF
R/W
D
2
R/W
DLE
D
1
ZiLOG
R/W
DAV
D
0