Z8622912SSG Zilog, Z8622912SSG Datasheet - Page 24

• Manufacturer Part Number: Z8622912SSG
• Description: IC CCD W/2ND I2C ADD 18-SOIC
• Manufacturer: Zilog
• Type: Video Decoderr

Specifications of Z8622912SSG

• Applications: Set-Top Boxes, TV
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 18-SOIC (7.5mm Width)
• Processor Series: Z8622x
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: CGROM
• Program Memory Size: 3.7 B
• Maximum Clock Frequency: 12 MHz
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Lead Free Status / Rohs Status: Details

5 ' 4 + # . % 1 / / 7 0 + % # 6 + 1 0 5 + 0 6 ' 4 ( # % '
Clock and Data Transitions.
are normally pulled High with a resistor. Data on the SDA
bus may only change during SCK Low time periods. Data
changes during SCK High periods indicate a start or stop
condition (Table 11) defined as:
Start Condition.
High as a start condition which must precede any other command.
Stop Condition.
High as a stop condition which terminates all communications.
Acknowledge.
to and from the Z86229 in eight-bit words. The instance of a ninth
bit generates an acknowledge. The device acknowledges the data
by pulling the SDA bus Low during the ninth bit. A Not AC-
Knowledge (NACK) is given by SDA=High during the ninth
clock time.
SPI Bus Operation
When the SMS pin is High, the Z86229 is in the SPI serial
control mode. The clock line should be tied to the SCK pin.
The DATA IN signal and DATA OUT signal from the mas-
ter device should be connected to the SDA and SDO pins,
respectively. The SEN pin is used to select the Z86229 when
there are multiple peripherals on the bus.
As noted above, when both the SMS and SEN pins are Low,
the part is in the RESET state. When the SPI bus is used in
a dedicated fashion between the master and the Z86229,
both the SEN and SMS pins would be tied High. The RESET
5 % -
. 1 9
* K I J
4
(
# #
$ 7 (
* &  5 6 #
5 7  5 6 #
* &  & # 6
5 7  & # 6
5 7  5 6 1
& *
+
All address and data words are serially transmitted
A Low-to-High transition of SDA, with a SCK
A High-to-Low transition of SDA, with a SCK
The SCK and SDA bus lines
Table 11. I
2
% Q P V K P W G F
C Serial Timing Min/Max
function would require that both of these pins be tied to the
NReset signal. To ensure synchronization, the master de-
vice should send the serial synchronization signal after the
reset is released.
When the SPI mode is used in a multiple peripheral envi-
ronment, the SEN pin is used as the Z86229 enable signal.
The SMS could then be used for the NReset signal as long
as the reset was only applied while SEN is Low. In this case,
there would be no requirement for the master device to send
a serial synchronization string after reset if there was at least
100 ns between the end of the reset and the start of the port
enable.
SDA (IN)
SDA (OUT)
SCK
t
SU.STA
t
HD.STA
t
AA
t
F
Figure 11. I
t
HD.DAT
t
High
2
C Serial Timing
t
Low
t
t
SU.DAT
DH
t
R
µ
µ
µ
µ
µ
µ
µ
µ
µ
t
BUF
t
ZiLOG
SU.STO