AD1892JRRL Analog Devices Inc, AD1892JRRL Datasheet - Page 4

• Manufacturer Part Number: AD1892JRRL
• Description: IC SAMPLE CONV W/RX 20BIT 28SOIC
• Manufacturer: Analog Devices Inc
• Type: Sample Rate Converterr

Specifications of AD1892JRRL

• Rohs Status: RoHS non-compliant
• Applications: Players, Recorders
• Voltage - Supply, Digital: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Voltage - Supply, Analog: -

AD1892 PIN LIST
Biphase-Mark Serial Input
Pin Name SOIC
RXP
RXN
Serial Output Interface
Pin Name SOIC
SDATA
BCLK
LRCLK
SYNC
Decoded Channel Status Outputs
Pin Name SOIC
CA
CB
AD1892
(continued from Page 1)
PRODUCT OVERVIEW (Continued)
In addition to the Q-channel subcode and Channel Status buff-
ers, the AD1892 includes two 8-bit control registers and two 8-
bit status registers. The output data interface may be configured
in left-justified, I
AD1892 includes hardware power-down/reset and mute control
inputs, and power-down/reset and mute may also be invoked
through write to bits in the control registers. The AD1892
operates from a master clock that must be synchronous with the
output sample rate at 512 F
(CRC) error detection is performed over the full 80 bits of the
received Q-channel subcode information in consumer mode, as
well as the full 192 bits of the received Channel Status informa-
tion in professional mode.
The AD1892 includes a SYNC input (Pin 23) that allows
multiple AD1892s in a system to be synchronized to a common
LEFT/RIGHT clock.
The AD1892 is offered in a 28-lead SOIC package. It operates
over the industrial temperature range from –40 C to +85 C
at a supply voltage from 4.5 V to 5.5 V. The only external
components required to support the AD1892 are power supply
decoupling capacitors.
13
14
24
26
25
23
21
20
2
S-justified and right-justified modes. The
I/O
I
I
I/O
O
O
O
I
I/O
O
O
S
. Cyclic Redundancy Coding
Description
Positive differential biphase-mark serial digital audio receiver input. 20 mV hysteresis.
Negative differential biphase-mark serial digital audio receiver input. 20 mV hysteresis.
Description
Serial output, MSB first, containing two channels of 16 to 20 bits (default) of twos-complement
data per channel, depending on control register settings. The data can be configured in I
(default), left-justified, and right-justified orientations, depending on control register settings. See
Figure 36 for timing.
Bit clock output for output data. Frequency is either 32 F
depending on control register settings. See Figure 36 for timing.
LEFT/RIGHT clock output for output data. Runs continuously and is a synchronous divide-down
from MCLK (MCLK/512). See Figure 36 for timing.
The SYNC input allows multiple AD1892s in a system to be phase and group delay synchronized to
the same LEFT/RIGHT clock. The SYNC signal resets internal AD1892 counters such that 512 MCLK
cycles after the falling edge of SYNC, the AD1892 data will be valid, and the AD1892 LRCLK signal
will change state. It is recommended that the SYNC input be used only when the AD1892 is in the
64
Description
In consumer or professional mode, CA is the inverse of Channel Status Bit 1, Byte 0 (C1, audio/
nonaudio). CA = 0 indicates nonaudio, CA = 1 indicates audio. CA = 0 can be used to indicate
Dolby AC-3 encoded data.
In consumer mode, CB is the inverse of Channel Status Bit 2, Byte 0 (C2, copy/copyright). CB = 0
indicates copy permitted/copyright not asserted; CB = 1 indicates copy inhibited/copyright asserted.
In professional mode, CB is defined as EM0, the least significant bit of the two bits that encodes the
emphasis status of the audio material.
F
SOUT
BCLK mode (default configuration). GND when not in use.
–4–
DEFINITIONS
Dynamic Range
The ratio of a full-scale input signal to the integrated noise in the
passband (0 kHz to 20 kHz), expressed in decibels (dB).
Dynamic range is measured with a –60 dB input signal and
“60 dB” arithmetically added to the result. This measurement
technique is consistent with the recommendations of the Audio
Engineering Society (AES17-1991) and the Electronic Industries
Association of Japan (EIAJ CP-307).
Total Harmonic Distortion + Noise
Total Harmonic Distortion plus Noise (THD+N) is defined as
the ratio of the square root of the sum of the squares of the
values of the harmonics and noise to the value of the fundamen-
tal input frequency. It is usually expressed in percent (%) or
decibels.
Interchannel Phase Deviation
Difference in input sampling times between stereo channels,
expressed as a phase difference in degrees between 1 kHz inputs.
Group Delay
The time interval required for the frequency components of an
input pulse to appear at the converter’s output, expressed in
milliseconds (ms). More precisely, the derivative of radian phase
with respect to radian frequency at a given frequency.
S
(packed mode) or 64 F
S
(default),
2
S-justified
REV. 0