ADV7181BCP Analog Devices Inc, ADV7181BCP Datasheet - Page 17

• Manufacturer Part Number: ADV7181BCP
• Description: IC VIDEO DECODER NTSC 64-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7181BCP

• Applications: Recorders, Set-Top Boxes
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Adc/dac Resolution: 9b
• Screening Level: Industrial
• Package Type: LFCSP EP
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-ADV7181BEB - BOARD EVALUATION FOR ADV7181
• Lead Free Status / RoHS Status: Compliant, Contains lead / RoHS non-compliant

Drive Strength Selection (Clock)
DR_STR_C[1:0] Address 0x0E [3:2]
The DR_STR_C[1:0] bits can be used to select the strength of
the clock signal output driver (LLC pin). For more information,
refer to the following sections:
•
•
Table 20. DR_STR_C Function
DR_STR_C[1:0]
00
01 (default)
10
11
Drive Strength Selection (Sync)
DR_STR_S[1:0] Address 0x0E [1:0]
The DR_STR_S[1:0] bits allow the user to select the strength of
the synchronization signals with which HS, VS, and F are
driven. For more information, refer to the following sections:
•
•
Table 21. DR_STR_S Function
DR_STR_S[1:0]
00
01 (default)
10
11
Drive Strength Selection (Sync)
Drive Strength Selection (Data)
Drive Strength Selection (Clock)
Drive Strength Selection (Data)
Low drive strength (1×).
Medium low drive strength (2×).
Low drive strength (1×).
Medium low drive strength (2×).
Description
Medium high drive strength (3×).
High drive strength (4×).
Description
Medium high drive strength (3×).
High drive strength (4×).
Rev. B | Page 17 of 104
Enable Subcarrier Frequency Lock Pin
EN_SFL_PIN Address 0x04 [1]
The EN_SFL_PIN bit enables the output of subcarrier lock
information (also known as GenLock) from the ADV7181 to an
encoder in a decoder-encoder back-to-back arrangement.
Table 22. EN_SFL_PIN
EN_SFL_PIN
0 (default)
1
Polarity LLC Pin
PCLK Address 0x37 [0]
The polarity of the clock that leaves the ADV7181 via the LLC
pin can be inverted using the PCLK bit.
Changing the polarity of the LLC clock output may be
necessary to meet the setup-and-hold time expectations of
follow-on chips.
Table 23. PCLK Function
PCLK
0
1 (default)
Description
Invert LLC output polarity.
LLC output polarity normal (as per the Timing
Diagrams).
Description
Subcarrier frequency lock output is disabled.
Subcarrier frequency lock information is
presented on the SFL pin.
ADV7181