CS493105-CLZ Cirrus Logic Inc, CS493105-CLZ Datasheet - Page 58

• Manufacturer Part Number: CS493105-CLZ
• Description: IC DECODER AUD MULTI STD 44PLCC
• Manufacturer: Cirrus Logic Inc
• Type: Audio Decoderr

Specifications of CS493105-CLZ

• Applications: DVD
• Voltage - Supply, Analog: 2.37 V ~ 2.63 V
• Voltage - Supply, Digital: 2.37 V ~ 2.63 V
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1670

The timing for an autoboot sequence is illustrated
in
RESET low and placing the decoder into reset. At
the rising edge of RESET, the ABOOT, WR, and
RD pins are sampled. If ABOOT is low when
sampled, and the WR and RD pins are set to
configure the device for serial communications, the
device will begin to autoboot (PSEL is a don’t care
for serial communications modes).
“Serial Communication” on page 36
procedure required for placing the CS493XX into a
serial communication mode in more detail. For a
more thorough description of ABOOT’s behavior
after the rising edge of RESET please refer to
Section 8.2.1, “Autoboot INTREQ Behavior” on
page 60
The EMOE pin of the CS493XX is used for two
purposes. It generates clock pulses for the latches,
and it is used in conjunction with EXTMEM to
enable the outputs of the ROM. The first three
rising edges of EMOE are used to latch address
bytes, as shown in the diagram. The fourth low
pulse of EMOE is used to enable the ROM outputs.
When both EXTMEM and EMOE go low, the
EMAD[7:0] pins of the DSP become inputs and
await the data coming from the ROM.
When comparing the memory system in
"External Memory Interface" on page 53
timing diagram of
Diagram" on page 58
discrepancy. The timing diagram shows three
address cycles, but there are only two latches in
the illustration of the memory architecture. This
difference is a result of code size limitations. The
application code is guaranteed to fit into a 32
Kilobyte space, which means that only 15 address
bits will actually be used for retrieving code from
58
Figure
35. The sequence is initiated by driving
Figure 35, "Autoboot Timing
EMAD7:0
EXTMEM
there may appear to be a
ABOOT
RESET
EMWR
EMOE
Figure 35. Autoboot Timing Diagram
discusses the
Section 6.1,
Figure 30,
to the
MA23:16
the ROM. Thus, the two latches catch the least
significant bytes, and the most significant byte is
dropped.
In autoboot mode, latching the most significant
byte would be perfectly valid since the most
significant bits are guaranteed to be zeros (the
three bytes represent a true 24-bit address).
The flow chart given in
Sequence"
interaction required by the microcontroller when
placing the DSP into autoboot mode. The host
must first drive the RESET line low.
After waiting for 175 ms, the application code
should be fully downloaded to the DSP, however
the designer should note that this time is typical
and may vary for each application code. During the
wait period, the host should ignore all INTREQ
behavior (mask the INTREQ interrupt). The host
can then verify that the code has successfully
initialized itself by sending a solicited read
command to the DSP to check for a known default
value.
Rd_Audio_Mgr_Request (0x090003) the host will
receive
0x000000). If the first read attempt returns an
incorrect value, a 5ms wait should be inserted and
the read should be repeated. If a second invalid
response is read, the entire boot process should
then be repeated. When the number returned
matches the default value for the variable read, the
host can be confident that the application is
resident in the DSP and awaiting further
instructions. An application code user’s guide
should be consulted for information about reading
a variable from the part.
Hardware configuration messages are used to
define the behavior of the DSP’s audio ports. A
MA15:8
Rd_Audio_Mgr_Response
For
on
MA7:0
CS49300 Family DSP
page
example,
Data7:0
59
Figure 36, "Autoboot
demonstrates
by
(0x890003,
DS339F7
sending
the