Z0220112VEGR3470 Zilog, Z0220112VEGR3470 Datasheet - Page 32

• Manufacturer Part Number: Z0220112VEGR3470
• Description: IC MODEM 2400BPS DSP AFE 44-PLCC
• Manufacturer: Zilog

Specifications of Z0220112VEGR3470

• Data Format: V.21, V.22, V.23, Bell 103, Bell 212A
• Baud Rates: 2.4k
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 18. REG7: HDLC Register
PS000904-0107
SYMBOL
EOF
RXERR
TEND
0
Notes:
1. All the bits in this register (REG 7) default to 0 at power up or after reset.
2. All undefined bits of this register are reserved. The host writes a 0 to all reserved bit positions when writing this
Bit
register. The host ignores the reserved bits when reading this register.
POSITION
REG 7, bit 0
REG 7, bit 1
REG 7, bit 2
REG 7,
bits 3–7
0
7
Reg7 Data Pump Register 7—
the data pump is in the HDLC FRAMING mode. These bits are valid only if BUFC-
TRL. bit
6
0
7
(HDLC) is
NAME AND DESCRIPTION
Receive End of Frame. The data pump sets EOF to 1 when an HDLC frame
has been completely received (that is, when frame data has been received
and a closing HDLC flag or HDLC Abort condition is received). If the frame
was correctly received, the data pump also sets Reg5, bit 1 (RXERROR) to
0, Reg5, bit 6 (RXI) to 1, and DATAP to 7EH. See Reg7, bit 1 (RXERROR)
for a description of CRC errors and HDLC Aborts. EOF reflects whether the
current register DATAP value indicates the end of receipt of an HDLC frame.
When the first data byte of the next HDLC frame is received, or if an HDLC
ABORT condition is received when no HDLC frame data was received, the
data pump sets EOF to 0. This condition may occur only 8 bit times after the
data pump sets EOF to 1.
Receive Error. If an HDLC frame contains a CRC error, or an HDLC Abort
condition is received, the data pump sets RXERROR to 1, Reg5, bit 6 (RXI)
to 1, and DATAP to the value of 7EH or FFH. If the frame had a CRC error,
DATAP has the value of 7EH. If an HDLC Abort condition was received,
DATAP is FFH. RXERROR reflects whether the current register DATAP
contains an error. When the first data byte of the next HDLC frame is
received, the data pump sets RXERROR to 0. This condition may occur only
8 bit times after the data pump set RXERROR to 1.
Transmit End of Frame. The data pump sets TEND to 1 when it closes an
HDLC frame that is transmitted. The data pump sets TEND to 0 after
transmitting the CRC bytes, when it starts transmitting the closing flag of the
HDLC frame. The data pump closes an HDLC frame when the host does not
provide data to transmit (see DATAP) in time to be included in the HDLC
frame.
Unused. Set these bits to 0.
5
0
1
. The host should refrain from writing Reg7 to avoid changing
4
0
These bits represent the state of HDLC frames when
3
0
V.22BIS Data Pump with Integrated AFE
TEND
2
RXERR
1
EOF
0
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