Z0220112VEGR3470 Zilog, Z0220112VEGR3470 Datasheet - Page 33
Z0220112VEGR3470
Manufacturer Part Number
Z0220112VEGR3470
Description
IC MODEM 2400BPS DSP AFE 44-PLCC
Manufacturer
Zilog
Specifications of Z0220112VEGR3470
Data Format
V.21, V.22, V.23, Bell 103, Bell 212A
Baud Rates
2.4k
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Package / Case
44-LCC (J-Lead)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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RAMI, RXI, and TXI Interrupts
PS000904-0107
the values of bit fields set by the data pump. Bits not defined above are reserved
or not available for use.
The host reads register Reg7 immediately before DATAP. The two CRC checksum
bytes in received HDLC frames are provided to the host.
At any reset, or when the host sets Config register, bits 0–6 (MODE) to 0
(STANDBY) the data pump sets TEND to
The three most significant bits in the RAM Control and data pump status registers
define the interrupt masks for RAMI, RXI, and TXI. A logical AND operation is
performed with the RAMIE, RXIE, and TXIE enable bits of the RAM Control regis-
ter and the corresponding interrupt bits in the DATA PUMP STATUS register. A log-
ical OR operation is performed on the outputs driving the HIRQ pin, providing an
interrupt to the host interrupt (See
Figure
V.22BIS Data Pump with Integrated AFE
0
9).
, RXERROR to
0
, and EOF to
0
.
29