AD2S83IP-REEL Analog Devices Inc, AD2S83IP-REEL Datasheet - Page 6

• Manufacturer Part Number: AD2S83IP-REEL
• Description: IC R/D CONV TRACKING 44PLCC T/R
• Manufacturer: Analog Devices Inc
• Type: R/D Converterr

Specifications of AD2S83IP-REEL

• Rohs Status: RoHS non-compliant
• Input Type: Parallel
• Output Type: Digital
• Interface: Parallel
• Current - Supply: 30mA
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC

AD2S83
CONNECTING THE CONVERTER
The power supply voltages connected to +V
should be +12 V dc and –12 V dc and must not be reversed.
The voltage applied to V
It is recommended that the decoupling capacitors are connected
in parallel between the power lines +V
GROUND adjacent to the converter. Recommended values are
100 nF (ceramic) and 10 µF (tantalum). Also capacitors of
100 nF and 10 µF should be connected between +V
DIGITAL GROUND adjacent to the converter.
Binary
Bits (N)
10
11
12
13
14
15
16
17
18
0
1
2
3
4
5
6
7
8
9
SIG GND
RIPPLE
CLOCK
+12V
–12V
Resolution
(N
COS
GND
131072
262144
SIN
16384
32768
65536
1024
2048
4096
8192
N
128
256
512
)
16
32
64
DATA
LOAD
1
2
4
8
SC1 SC2
Bit Weight Table
Degrees
/Bit
360.0
180.0
90.0
45.0
22.5
11.25
L
0.3515625
0.1757813
0.0878906
0.0439453
5.625
2.8125
1.40625
0.703125
0.0219727
0.0109836
0.0054932
0.0027466
0.0013733
can be +5 V dc to +V
A2
A1
ENABLE
16-BIT UP/DOWN COUNTER
SWITCHING
SEGMENT
Minutes
/Bit
21600.0
10800.0
5400.0
2700.0
1350.0
S
675.0
337.5
168.75
OUTPUT DATA LATCH
, –V
84.375
42.1875
21.09375
10.546875
5.273438
2.636719
1.318359
0.659180
0.329590
0.164795
0.082397
16 DATA BITS
S
S
and ANALOG
and –V
S
.
R - 2R DAC
Seconds
/Bit
1296000.0
648000.0
324000.0
162000.0
L
81000.0
40500.0
20250.0
10125.0
S
5062.5
2531.25
1265.625
and
316.40625
158.20313
632.8125
pins
79.10156
39.55078
19.77539
9.88770
4.94385
AC ERROR O/P
SELECT
BYTE
A3
AD2S83
5V
C1
R1
HF FILTER
When more than one converter is used on a card, separate de-
coupling capacitors should be used for each converter.
The resolver connections should be made to the SIN and COS
inputs, REFERENCE INPUT and SIGNAL GROUND as
shown in Figure 11 and described in the Connecting the
Resolver section.
The two signal ground wires from the resolver should be joined
at the SIGNAL GROUND pin of the converter to minimize the
coupling between the sine and cosine signals. For this reason it
is also recommended that the resolver is connected using indi-
vidually screened twisted pair cables with the sine, cosine and
reference signals twisted separately.
SIGNAL GROUND and ANALOG GROUND are connected
internally. ANALOG GROUND and DIGITAL GROUND
must be connected externally and as close to the converter as
possible.
The external components required should be connected as
shown in Figure 1.
CONVERTER RESOLUTION
Two major areas of the AD2S83 specification can be selected by
the user to optimize the total system performance. The resolu-
tion of the digital output is set by the logic state of the inputs
SC1 and SC2 to be 10, 12, 14 or 16 bits; and the dynamic char-
acteristics of bandwidth and tracking rate are selected by the
choice of external components.
The choice of the resolution will affect the values of R4 and R6
which scale the inputs to the integrator and the VCO respec-
tively (see Component Selection section). If the resolution is
changed, then new values of R4 and R6 must be switched into
the circuit.
Note: When changing resolution under dynamic conditions, do
it when the BUSY is low, i.e., when data is not changing.
GND
DIG
BUSY
R2
C2
SENSITIVE
DETECTOR
PHASE
VCO + DATA
DIRECTION
TRANSFER
REFERENCE
LOGIC
I/P
C3
DEMOD
O/P
R3
INHIBIT
INTEGRATOR
R4
+12V
VCO
VCO
O/P
O/P
I/P
OFFSET ADJUST
INTEGRATOR
R9
I/P
150pF
R7
3K3
C7
C6
390pF
BANDWIDTH
SELECTION
R8
R6
–12V
TRACKING
RATE
SELECTION
C5
C4
R5
VELOCITY
SIGNAL