PI2EQX5864CZFE Pericom Semiconductor, PI2EQX5864CZFE Datasheet - Page 5

• Manufacturer Part Number: PI2EQX5864CZFE
• Description: IC PCI-E REDRIVER 56TQFN
• Manufacturer: Pericom Semiconductor
• Series: ReDriver™r
• Type: Redriverr

Specifications of PI2EQX5864CZFE

• Tx/rx Type: CML
• Capacitance - Input: 50pF
• Voltage - Supply: 1.15 V ~ 1.25 V
• Current - Supply: 800mA
• Mounting Type: Surface Mount
• Package / Case: 56-TQFN
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Compliant

Receiver Detect
Automatic Receiver Detection is a feature that can set the number of active channels. By sensing the presence of a load device
on the output, the channel can be automatically enabled for operation. This allows the PI2EQX5864C to confi gure itself properly
depending on the devices it is communicating with, whether it is a 4-lane, 3-lane, 2-lane or just 1-lane device or adapter card.
Receiver Detect is enabled by the RXD_A, or RXD_B pins, or alternatively via I
to low, the Receiver Detect operation for that group of channels is disabled, and those channels go directly to 50-Ohm input termi-
nation to ground and 50-Ohm output termination to VDD (for a valid differential channel input level) or to 2K-Ohm (if the signal
level is less than the threshold level).
The RESET# input is used to reset the receiver detect state machine to its initial state. The start of the receiver detect cycle starts
when RESET# transitions from low to high.
When a Receiver Detect cycle begins the differential channel pins are enabled with a 2K-Ohm pull-up to VDD. A 50-Ohm Receiv-
er termination will change the pin level. This pin level is evaluated after a fi xed time-out, and the channel is then set into the proper
operating state. The register bits RX50_Ax and RX50_Bx represent the receiver detect result for their specifi c channels.
The I/O operation table summarizes the relationships and operation of receiver detect and other signals involved with I/O control.
I/O Operation Control
Control Inputs
RXD_x
X
0
0
0
1
1
1
1
09-0002
RESET#
X
0
1
1
0
1
1
1
RX50
X
X
X
X
X
0
1
1
Detection
States
SIG_x
X
X
X
X
0
1
0
1
Hi-Z
Hi-Z
50-Ohm pull-
down
50-Ohm pull-
down
Hi-Z
Hi-Z
50-Ohm pull-
down
50-Ohm pull-
down
Input Termination Output Termination
Data Channel I/O
Hi-Z
2K-Ohm pull-up
2K-Ohm pull-up
50-Ohm pull-up
2K-Ohm pull-up
2K-Ohm pull-up
2K-Ohm pull-up
50-Ohm pull-up
5
with Equalization, Emphasis and I
2
5.0Gbps 4-Lane PCIe
C programming. When RXD_A or RXD_B is set
Full IC power down, all channels disabled
Channel disabled, output pulls to VDD.
Receiver detect reset
Channel enabled, no input signal, output
pulls to VDD. Receiver detect disabled
Channel enabled, valid input signal de-
tected, output driving. Receiver detect
disabled.
Channel disabled. Receiver detect reset.
Channel disabled, output pulls to VDD. Re-
ceiver detect enabled, no receiver detected.
Channel inactive, output pulls to VDD.
Receiver detect enabled, receiver detected.
No input signal
Channel active, valid input signal detected,
output driving. Receiver detect enabled,
load detected.
Mode
®
2.0 ReDdriver™
PS8934D
PI2EQX5864C
2
C Control
07/08/09