LA-ISPPAC-POWR1014-01TN48E Lattice, LA-ISPPAC-POWR1014-01TN48E Datasheet - Page 27

• Manufacturer Part Number: LA-ISPPAC-POWR1014-01TN48E
• Description: IC, PROG POWER SUPPLY SUPERVISOR TQFP-48
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of LA-ISPPAC-POWR1014-01TN48E

• Input Voltage: 4.5V
• Supply Voltage Range: 2.8V To 3.96
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +105°C
• No. Of Macrocells: 24
• Termination Type: SMD
• Supply Voltage Min: 2.8V
• Rohs Compliant: Yes
• Applications: General Purpose
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 20mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Filter Terminals: SMD
• Frequency: 25MHz
• Input Voltage Primary Max: 4.5V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
command (Waiting for the DONE bit to be set to 1). An alternative would be to wait for a minimum specified time
(see T
Note that if the I
conversion is to wait the minimum specified time (T
than that cannot be guaranteed. In other words, if the I
not assert even though a valid conversion result is available.
To insure every ADC conversion result is valid, preferred operation is to clock I
DONE bit status or wait for the full T
request is placed before the current conversion is complete, the DONE bit will be set to 1 only after the second
request is complete.
The status of the digital input lines may also be monitored and controlled through I
the I
register, while input values to the PLD array may be set by writing to the INPUT_VALUE register. To be able to set
an input value for the PLD array, the input multiplexer associated with that bit needs to be set to the I
ting in E
Figure 19. I
The digital outputs may also be monitored and controlled through the I
tus of any given digital output may be read by reading the contents of the associated OUTPUT_STATUS[1:0] regis-
ter. Note that in the case of the outputs, the status reflected by these registers reflects the logic signal used to drive
the pin, and does not sample the actual level present on the output pin. For example, if an output is set high but is
2
C interface to the IN[1:4] digital input lines. The input status may be monitored by reading the INPUT_STATUS
CONVERT
2
CMOS memory otherwise the PLD will receive its input from the INx pin.
2
C Digital Input Interface
value in the specifications) and disregard checking the DONE bit.
2
C clock rate falls below 50kHz (see F
0x11 - INPUT_VALUE (Read/Write)
0x06 - INPUT_STATUS (Read Only)
IN[2..4]
b7
b7
X
1
IN1
USERJTAG
b6
b6
X
1
CONVERT
Bit
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Input_Value
b5
b5
PLD Output/Input_Value Register Select
X
1
3
3
time period between subsequent ADC convert commands. If an I
I
2
CONVERT
C Interface Unit
b4
b4
MUX
MUX
1
X
(E 2 Configuration)
I 2 C
2
C clock rate is less than 50kHz, the DONE bit may or may
27
note in specifications), the only way to insure a valid ADC
3
2
IN4
b3
b3
), as the operation of the DONE bit at clock rates lower
I4
Input_Status
3
IN3
b2
b2
I3
2
C interface, as shown in Figure 20. The sta-
IN2
b1
b1
I2
2
C at more than 50kHz and verify
Array
PLD
2
C commands. Figure 19 shows
IN1
b0
b0
X
2
C register set-
2
C