LA-ISPPAC-POWR1014-01TN48E Lattice, LA-ISPPAC-POWR1014-01TN48E Datasheet - Page 37

• Manufacturer Part Number: LA-ISPPAC-POWR1014-01TN48E
• Description: IC, PROG POWER SUPPLY SUPERVISOR TQFP-48
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of LA-ISPPAC-POWR1014-01TN48E

• Input Voltage: 4.5V
• Supply Voltage Range: 2.8V To 3.96
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +105°C
• No. Of Macrocells: 24
• Termination Type: SMD
• Supply Voltage Min: 2.8V
• Rohs Compliant: Yes
• Applications: General Purpose
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 20mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Filter Terminals: SMD
• Frequency: 25MHz
• Input Voltage Primary Max: 4.5V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 11. LA-ispPAC-POWR1014/A TAP Instruction Table
BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and
TDO and allows serial data to be transferred through the device without affecting the operation of the LA-ispPAC-
POWR1014/A. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (11111111).
The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI
and TDO. The LA-ispPAC-POWR1014/A has no boundary scan register, so for compatibility it defaults to the
BYPASS mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown
in Table 11.
The EXTEST (external test) instruction is required and would normally place the device into an external boundary
test mode while also enabling the boundary scan register to be connected between TDI and TDO. Again, since the
LA-ispPAC-POWR1014/A has no boundary scan logic, the device is put in the BYPASS mode to ensure specifica-
tion compatibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros (00000000).
BULK_ERASE
BYPASS
DISCHARGE
ERASE_DONE_BIT
EXTEST
IDCODE
OUTPUTS_HIGHZ
SAMPLE/PRELOAD
PROGRAM_DISABLE
PROGRAM_DONE_BIT
PROGRAM_ENABLE
PROGRAM_SECURITY
RESET
IN1_RESET_JTAG_BIT
IN1_SET_JTAG_BIT
CFG_ADDRESS
CFG_DATA_SHIFT
CFG_ERASE
CFG_PROGRAM
CFG_VERIFY
PLD_ADDRESS_SHIFT
PLD_DATA_SHIFT
PLD_INIT_ADDR_FOR_PROG_INCR
PLD_PROG_INCR
PLD_PROGRAM
PLD_VERIFY
PLD_VERIFY_INCR
UES_PROGRAM
UES_READ
Instruction
Command
0000 0011
1111 1111
0001 0100
0010 0100
0000 0000
0001 0110
0001 1000
0001 1110
0010 1111
0001 0101
0000 1001
0010 0010
0001 0010
0001 0011
0010 1011
0010 1101
0010 1001
0010 1110
0010 1000
0000 0001
0000 0010
0010 0001
0010 0111
0000 0111
0000 1010
0010 1010
0001 1010
0001 0111
00011100
Code
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Bulk erase device
Bypass - connect TDO to TDI
Fast VPP discharge
Erases ‘Done’ bit only
Bypass - connect TDO to TDI
Read contents of manufacturer ID code (32 bits)
Force all outputs to High-Z state, FET outputs pulled low
Sample/Preload. Default to bypass.
Disable program mode
Programs the Done bit
Enable program mode
Program security fuse
Resets device (refer to the RESETb Signal, RESET Command via
JTAG or I
Reset the JTAG bit associated with IN1 pin to 0
Set the JTAG bit associated with IN1 pin to 1
Select non-PLD address register
Non-PLD data shift
ERASE Just the Non PLD configuration
Non-PLD program
VRIFY non-PLD fusemap data
PLD_Address register (109 bits)
PLD_Data register (123 Bits)
Program column register to E
Program PLD data register to E
Verifies PLD column data
Load column register from E
Program UES bits into E
Read contents of UES register from E
Initialize the address register for auto increment
37
2
C section of this data sheet)
2
2
Comments
2
and auto increment address register
and auto increment address register
2
2
(32 bits)