HCTL-2021-PLC Avago Technologies US Inc., HCTL-2021-PLC Datasheet - Page 6

• Manufacturer Part Number: HCTL-2021-PLC
• Description: IC DECODER/COUNTER 16BIT 20-PLCC
• Manufacturer: Avago Technologies US Inc.

Specifications of HCTL-2021-PLC

• Package / Case: 20-PLCC
• Applications: Encoder to Microprocessor
• Interface: 8-Bit Tristate
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 516-1884-5; HCTL-2021-PLC

Switching Characteristics
Table 5. Switching Characteristics Max/Min specifications at V
Figure 1. Reset Waveform
Figure 2: Waveforms for Positive Clock Edge Related Delays
6
Symbol Description
1
2
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
4
tCLK
tCHH
tCD
tODE
tODZ
tSDV
tCLH
tSS
tOS
tSH
tOH
tRST
tDCD
tDSD
tDOD
tUDD
tCHD
tCLD
tUDH
tUDCS
tUDCH
Pulse width, clock high
Delay time, rising edge of clock to valid, updated count information on
D0-7
Delay time, OE fall to valid data
Delay time, OE rise to Hi-Z state on D0-7
Delay time, SEL valid to stable, selected data byte (delay to High Byte
Pulse width, clock low
Hold time, SEL after clock fall
Hold time, OE after clock fall
Pulse width, RST low
Hold time, last position count stable on D0-7 after clock rise
Hold time, last data byte stable after next SEL state change
Hold time, data byte stable after OE rise
Delay time, U/D valid after clock rise
Delay time, CNTDCDR or CNTCAS high after clock rise
Delay time, CNTDCDRor CNTCAS low after clock fall
Hold time, U/D stable after clock rise
Hold time, U/D stable after CNTDCDR or CNTCAS rise
Clock Period
= delay to Low Byte)
Setup time, SEL before clock fall
Setup time, OEN before clock fall
Setup time, U/D valid before CNTDCDR or CNTCAS rise
DD
= 5.0 ± 5%, T
A
= -40 to +85
O
C, C
L
= 40 pf
Min.
70
20
0
0
10
10
10
10
28
28
20
28
tCLK-45
tCLK-45
Max.
65
65
65
40
45
45
45
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns