W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet
W83627UHG
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W83627UHG Summary of contents
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... W83627UHG WINBOND LPC I/O Date: May/25/2007 Revision: 1.0 ...
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... W83627UHG Data Sheet Revision History PAGES DATES VERSION 1 NA 9/14/2006 2 NA 11/29/2006 NA 05/25/2007 3 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury ...
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... Software Programming Example ....................................................................................24 7. HARDWARE MONITOR ........................................................................................................... 26 7.1 General Description ...................................................................................................... 26 7.2 Access Interfaces.......................................................................................................... 26 7.2.1 LPC Interface .................................................................................................................27 2 7.2 Interface....................................................................................................................29 7.3 Analog Inputs ................................................................................................................ 31 7.3.1 Voltages Over 2.048 V or Less Than 0 V .......................................................................32 7.3.2 Voltage Detection ...........................................................................................................32 7.3.3 Temperature Sensing .....................................................................................................33 7.4 SST Command Summary............................................................................................. 35 7.4.1 Command Summary.......................................................................................................36 W83627UHG -II- ...
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... Reserved Registers - Index 17h (Bank 0) .................................................................... 63 8.27 OVT# Configuration Register - Index 18h (Bank 0)...................................................... 63 8.28 Reserved Registers - Index 19h ~ 1Fh (Bank 0) .......................................................... 64 Value RAM ⎯ Index 20h ~ 3Fh (Bank 0) ..................................................................... 64 8.29 TM Control...................................................................................................42 -III- W83627UHG Publication Release Date: May 25, 2007 Revision 1.0 ...
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... Reserved Registers - Index 6Dh (Bank 0).................................................................... 79 8.69 Reserved Registers - Index 6Eh (Bank 0) .................................................................... 79 8.70 CPUTIN/PECI Temperature (High Byte) Register - Index 50h (Bank 1) ...................... 79 8.71 CPUTIN/PECI Temperature (Low Byte) Register - Index 51h (Bank 1)....................... 79 8.72 CPUTIN Configuration Register - Index 52h (Bank 1).................................................. 80 W83627UHG -IV- ...
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... Main Status Register (MS Register) (Read base address + 4).....................................102 9.3.6 Data Rate Register (DR Register) (Write base address + 4) ........................................103 9.3.7 FIFO Register (R/W base address + 5) ........................................................................105 9.3.8 Digital Input Register (DI Register) (Read base address + 7).......................................107 W83627UHG Publication Release Date: May 25, 2007 -V- Revision 1.0 ...
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... KEYBOARD CONTROLLER................................................................................................... 132 12.1 Output Buffer............................................................................................................... 132 12.2 Input Buffer ................................................................................................................. 132 12.3 Status Register ........................................................................................................... 133 12.4 Commands.................................................................................................................. 134 12.5 Hardware GATEA20/Keyboard Reset Control Logic.................................................. 135 12.5.1 KB Control Register (Logic Device 5, CR-F0) ............................................................135 12.5.2 Port 92 Control Register (Default Value = 0x24) ........................................................137 W83627UHG -VI- ...
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... Absolute Maximum Ratings ........................................................................................ 194 18.2 DC CHARACTERISTICS............................................................................................ 194 18.3 AC CHARACTERISTICS............................................................................................ 199 18.3.1 Power On / Off Timing ................................................................................................199 18.3.2 AC Power Failure Resume Timing .............................................................................200 18.3.3 Clock Input Timing......................................................................................................205 18.3.4 PECI and SST Timing ................................................................................................206 W83627UHG Publication Release Date: May 25, 2007 -VII- Revision 1.0 ...
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... UART/Parallel Port .....................................................................................................209 18.3.8 Parallel Port Mode Parameters ..................................................................................211 18.3.9 Parallel Port ................................................................................................................212 18.3.10 KBC Timing Parameters...........................................................................................221 18.3.11 GPIO Timing Parameters .........................................................................................224 18.4 LRESET Timing .......................................................................................................... 225 19. TOP MARKING SPECIFICATION .......................................................................................... 226 20. PACKAGE SPECIFICATION .................................................................................................. 227 APPENDIX – ABBREVIATIONS ......................................................................................................... 228 W83627UHG -VIII- ...
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... Figure 7-2 Serial Bus Write to Internal Address Register Followed by the Data Byte .................... 29 Figure 7-3 Serial Bus Read from Internal Address Register........................................................... 30 Figure 7-4 Analog Inputs and Application Circuit of the W83627UHG ........................................... 31 Figure 7-5 Monitoring Temperature from Thermistor...................................................................... 33 Figure 7-6 Monitoring Temperature from Thermal Diode (Voltage Mode)...................................... 34 Figure 7-7 Monitoring Temperature from Thermal Diode ...
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... Table 13-2 Definitions of Mouse Wake-Up Events ....................................................................... 142 Table 13-3 Timing and Voltage Parameters of RSMRST# ........................................................... 143 Table 14-1 SERIRQ Sampling Periods ......................................................................................... 146 Table 16-1 Relative Control Registers of GPIO 25, 26 and 27 that Support Wake-Up Function . 149 Table 16-2 GPIO Register Addresses........................................................................................... 150 W83627UHG TM I Mode................................................................ 44 TM III Mode ................................................................ 48 TM III Control Mode ...
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... GENERAL DESCRIPTION The W83627UHG is a member of Winbond's Super I/O product line. This family features the LPC (Low Pin Count) interface. This interface is more economical than its ISA counterpart because it has approximately forty pins fewer, yet still provides as great performance. In addition, the improvement allows even more efficient operation of software, BIOS and device drivers ...
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... Loop-back controls for communications link fault isolation --- Break, parity, overrun, framing error simulation Programmable baud rate generator allows division of clock source by any value from -1) Maximum baud rate for clock source 14.769 MHz 921K bps. The baud rate at 24 MHz is 1.5M bps. W83627UHG -2- ...
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... Programmable hysteresis and setting points for all monitored items • Over-temperature indicator output • Issue SMI#, OVT# to activate system protection TM firmware TM TM ” modes and S F III functions MART AN TM mode -3- W83627UHG “Thermal Cruise MART AN Publication Release Date: May 25, 2007 Revision 1.0 TM ” ...
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... On Now Wake-Up from all of the ACPI sleeping states (S1-S5) Simple Serial Transport™ Interface SST temperature and voltage Combination Sensor command support Support SST 0.9 Specification PECI Interface PECI Host Support PECI 1.0 Specification Support 4 CPU addresses and 2 domains per CPU address Package 128-pin QFP Pb-free / RoHS TM Support -4- W83627UHG ...
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... LPC Interface GPIO FDC PECI UART A, B, SST IR HM PRT KBC ACPI Figure 3-1 W83627UHG Block Diagram -5- W83627UHG Floppy drive interface signals Serial port A, B,C,D,E,F interface signals IRRX IRTX Printer port interface signals Publication Release Date: May 25, 2007 Revision 1.0 ...
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... RTSE#/GP55 127 127 DTRE#/GP54 DTRE#/GP54 128 128 5VCC 5VCC Vtt Vtt VSB VSB VBAT VBAT W83627UHG W83627UHG 5VCC 5VCC Figure 4-1 W83627UHG Pin Layout -6- W83627UHG 64 64 SUSLED SUSLED 63 63 KDAT KDAT VSB VSB 62 62 KCLK KCLK 61 61 5VSB ...
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... OD - Open-drain output pin with 12mA sink capability Open-drain output pin with 24mA sink capability Output pin with 8mA source-sink capability Output pin with 12mA source-sink capability Output pin with 24mA source-sink capability 24 W83627UHG Publication Release Date: May 25, 2007 -7- Revision 1.0 ...
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... UART. Drive Select A. When set to 0, this pin enables disk drive A. This is an open-drain output. UART F Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. -8- W83627UHG DESCRIPTION DESCRIPTION ...
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... Floppy Drive compatibility. General purpose I/O port 6 bit 2. The read-data input signal from the FDD. This input pin needs to connect a pulled-up 1-KΩ resistor to 5V for Floppy Drive compatibility. General purpose I/O port 6 bit 1. Publication Release Date: May 25, 2007 -9- W83627UHG Revision 1.0 ...
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... See the description of the parallel port for the definition of this pin in ECP and EPP modes. PRINTER MODE: SLIN# Output line for detection of printer selection. See the description of the parallel port for the definition of this pin in ECP and EPP modes. -10- W83627UHG ...
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... Parallel port data bus bit 6. See the description of the parallel port for the definition of this pin in ECP and EPP modes. PRINTER MODE: PD7 Parallel port data bus bit 7. See the description of the parallel port for the definition of this pin in ECP and EPP modes. -11- W83627UHG Publication Release Date: May 25, 2007 Revision 1.0 ...
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... Data Set Ready. An active-low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. General-purpose I/O port 3 bit 6. Data Set Ready. An active-low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. General-purpose I/O port 4 bit 6. -12- W83627UHG ...
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... General-purpose I/O port 5 bit 5. UART F Request To Send. An active-low signal informs the modem or data set that the controller is ready to send data. Drive Select A. When set to 0, this pin enables disk drive A. This is an open drain output. -13- W83627UHG Publication Release Date: May 25, 2007 Revision 1.0 ...
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... IR Receiver input. General-purpose I/O port 1 bit 3. Serial Input. This pin is used to receive serial data through the communication link. General-purpose I/O port 3 bit 3. Serial Input. This pin is used to receive serial data through the communication link. General-purpose I/O port 4 bit 3. -14- W83627UHG ...
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... General-purpose I/O port 5 bit 2. 8 UART F Serial Output. This pin is used to transmit serial data out to the communication link. Write data. This logic low open drain writes pre-compensation serial data to the selected FDD. An open drain output. -15- W83627UHG Publication Release Date: May 25, 2007 Revision 1.0 ...
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... General-purpose I/O port 5 bit 0. Ring Indicator. An active-low signal indicates that a ring signal is being received from the modem or data set. Head select. This open drain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side 1 -16- W83627UHG ...
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... General-purpose I/O port 2 bit 1. 12t CASE OPEN Detection. An active-low input from an external device when the case is open. This signal can be latched if pin VBAT is connected to the battery, even if the W83627UHG is t turned off. Pull up a 2-MΩ resistor to VBAT is recommended if useless. Analog Inputs for voltage measurement (Range 2.048 V) Analog Inputs for voltage measurement (Range ...
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... Resume reset signal output. 12 System S3 state input. t Power Supply on-off Output. 12 This pin generates the PWROK signal while 5VCC comes in. 12 Serial Bus clock. ts General-purpose I/O port 2 bit 5. 12ts Serial bus bi-directional Data. 12t General-purpose I/O port 2 bit 6. 12t -18- W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION ...
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... General-purpose I/O port 2 bit 5. 12ts IN Serial Bus clock. ts General-purpose I/O port 2 bit 6. 12t Serial bus bi-directional data. 12t General-purpose I/O port 2 bit 7. 12t -19- W83627UHG POWER SOURCE 5VSB 5VSB 5VCC 5VCC 5VCC 5VCC DESCRIPTION Publication Release Date: May 25, 2007 Revision 1.0 ...
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... V power supply for the digital circuit. +3.3V power supply for driving 3V on the host interface. Analog +5 V power input. Internally supply to all analog circuits. Analog ground. The ground reference for all analog input. Internally connected to all analog circuits. Ground. ® INTEL CPU Vtt power. -20- W83627UHG DESCRIPTION ...
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... CONFIGURATION REGISTER ACCESS PROTOCOL The W83627UHG uses Super I/O protocol to access configuration registers to set up different types of configurations. The W83627UHG has totally fifteen Logical Devices (from Logical Device 0 to Logical Device F with the exception of Logical Device 4 for backward compatibility) corresponding to fifteen individual functions: FDC (Logical Device 0), Parallel Port (Logical Device 1), UARTA (Logical Device 2), UARTB (Logical Device 3), Keyboard Controller (Logical Device 5), UARTC (Logical Device 6), GPIO3, 4 (Logical Device 7), WDTO# & ...
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... UART A UART B Reserved Keyboard Controller UART C GPIO 3, 4 GPIO 1, 2 ACPI Hardware Monitor PECI & SST UART C UART D UART E -22- W83627UHG I/O BASE DEFAULT ADDRESS VALUE 100h ~ FF8h 3F0h 100h ~ FF8h 378h 100h ~ FF8h 3F8h 100h ~ FF8h 2F8h 100h ~ FF8h 60h/64h ...
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... Configuration Sequence program the W83627UHG configuration registers, the following configuration procedures must be followed in sequence: (1). Enter the Extended Function Mode. (2). Configure the configuration registers. (3). Exit the Extended Function Mode. 6.1.1 Enter the Extended Function Mode To place the chip into the Extended Function Mode, two successive writes of 0x87 must be applied to Extended Function Enable Registers (EFERs, i ...
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... Configure Logical Device 1, Configuration Register CRF0 ;----------------------------------------------------------------------------- MOV DX, 2EH MOV AL, 07H OUT DX point to Logical Device Number Reg. MOV DX, 2FH MOV AL, 01H OUT DX select Logical Device 1 ; MOV DX, 2EH MOV AL, F0H OUT DX select CRF0 MOV DX, 2FH MOV AL, 3CH OUT DX update CRF0 with value 3CH W83627UHG -24- ...
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... R/W 00h R/W 00h Reserved R/W 02h R/W 00h R/W 00h R/W 00h -25- W83627UHG DESCRIPTION Software Reset Logical Device Chip ID, MSB Chip ID, LSB Device Power Down Device Power Down Global Option Interface Tri-state Enable Global Option Global Option Multi-function Pin Selection ...
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... The W83627UHG provides hardware access to all monitored parameters through the LPC or I interface and software access through application software, such as Winbond’s Hardware Doctor BIOS. In addition, the W83627UHG can generate pop-up warnings or beep tones when a parameter goes outside of a user-specified range. ...
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... CR60 and CR61 accessed using the Super I/O protocol as described in Chapter 6. Due to the number of internal registers necessary to separate the register sets into “banks” specified by register 4Eh. The structure of the internal registers is shown in the following figure. W83627UHG Publication Release Date: May 25, 2007 -27- ...
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... Temperature Sensor Type Configuration & Fan Divisor Registers 59h,5Dh BANK 0 Cirtical Tempature and Curren mode enable 5Eh BANK 0 Smart Fan Configuration Registers 60h~6Ah -28- W83627UHG BANK 0 FANOUT Critical Temperature 6Bh~6Eh BANK 1 CPUTIN Temperature Control/Stauts Registers 50h~56h BANK 4 Interrupt Status & SMI# Mask Registers 50h~51h ...
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... C interface is a second, parallel port into the internal registers of the hardware monitor function block. The interface is totally compatible with the industry-standard I components that are also compatible to read the internal registers of the W83627UHG hardware monitor and control fan speeds. The address of the I index 48h (which is accessed by the index/data pair at I/O address typically at 295h/296h) ...
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... Frame 3 Repeat Serial Bus Address Byte start by Master Figure 7-3 Serial Bus Read from Internal Address Register R Ack by 627UHG R Ack Frame 4 by 627UHG Data Byte 0 -30- W83627UHG Ack Frame 2 by 627UHG Internal Index Register Byte Ack Stop by by Master Master ...
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... Negative Voltage Input V2 10K@25 C, beta=3435K Figure 7-4 Analog Inputs and Application Circuit of the W83627UHG As illustrated in the figure above, other connections may require some external circuits. The rest of this section provides more information about voltages outside the range of the 8-bit ADC, CPU Vcore ...
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... The W83627UHG uses the same approach. Pins 12 and 97 provide two functions. One, these pins are connected to 5VCC supply internal (digital / analog) power to the W83627UHG. Two, these pins monitor 5VCC. The W83627UHG has two internal, 80-KΩ and 20-KΩ, serial resistors that reduce the ADC-input voltage ...
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... W83627UHG 9-BIT DIGITAL OUTPUT 9-BIT BINARY 9-BIT HEX 0,1111,1010 0FAh 0,0011,0010 032h 0,0000,0010 002h 0,0000,0001 001h 0,0000,0000 000h 1,1111,1111 1FFh 1,1111,1110 1FFh 1,1100,1110 1CEh 1,1001,0010 192h Pin 102 W83627UHG Pin 103 Pin 104 Publication Release Date: May 25, 2007 Revision 1.0 ...
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... Monitor Temperature from Thermal Diode (Voltage Mode) The thermal diode D- pin is connected to AGND (pin 105), and the D+ pin is connected to the temperature sensor pin in the W83627UHG. A 15-KΩ resistor is connected to VREF to supply the bias current for the diode, and the 2200-pF, bypass capacitor is added to filter high-frequency noise. The configuration registers to select a thermal diode temperature sensor and the measurement method are found at Bank 0, Index 59h, 5Dh, and 5Eh ...
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... SST Command Summary The W83627UHG can act as an SST peripheral or slave and output the results of the Analog to Digital Converter onto the SST bus. SST is a new, popular standard to communicate temperature and voltage information from around the PC motherboard to report on the status of the system and control cooling fans and other safety mechanisms ...
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... Command Summary The W83627UHG supports SST commands as shown in the following table: COMMAND ResetDevice() GetDIB() GetIntTemp() GetExtTemp() GetAllTemps() GetVolt12V() GetVolt5V() GetVolt3p3V() GetVolt2p5V() GetVoltVccp() GetAllVoltages() Table 7-2 SST Command Summary This command is used to recover from serious hardware or bus error. Support 8-byte and 16-byte read length ...
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... Voltage Data Format The W83627UHG can return five (5) voltage values through the SST interface. The voltage data format is 16-bit two’s-complement binary. The relation between the 2-byte data and the monitored voltage is listed below: 1) CPUVCORE (pin 101) = Decimal[2-byte data by GetVoltVccp 1024 volts 2) 5VCC (pin 12) = Decimal[2-byte data by GetVolt5V()] / 1024 volts 3) “ ...
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... W83627UHG to access the agent. The power-on default is disabled. After an agent is enabled, the W83627UHG issues PING and GetTemp commands to obtain the PECI temperature. 5. Since the PECI temperature is a relative value, the W83627UHG provides registers for each PECI Agent to convert the relative value to a more traditional “absolute” format. The TBase registers (Logical Device C, CR[E1h]~CR[E4h]) store the “ ...
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... A warning flag register at Logical Device C, CR[E8h] bit (7..4) is designed for each PECI Agent to report whether the W83627UHG (PECI host) detects the PECI client or not and whether the PECI client returns invalid FCS values from the polling for three successive times. ...
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... Fan Speed Measurement The W83627UHG can measure fan speed for fans equipped with tachometer outputs. The tachometer signals should be set to TTL-level, and the maximum input voltage cannot exceed + the tachometer signal exceeds + external trimming circuit should be added to reduce the voltage accordingly ...
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... Fan Speed Control The W83627UHG has two output pins for fan control, each of which offers PWM duty cycle and DC voltage to control the fan speed. The output type (PWM or DC) of each pin is configured by Bank0 Index 04h, bits For PWM, the duty cycle is programmed by eight-bit registers at Bank0 Index 01h and Index 03h. The ...
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... TM 7.6.3 SMART FAN Control The W83627UHG supports two S TM Cruise mode—and S F MART features are enabled, fan output starts from the previous setting in Bank0 Index 01h MART AN and Index 03h. There are two pairs of temperature sensors and fan outputs in S figure below. ...
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... The following figures illustrate two examples of Thermal Cruise Figure 7-10 Mechanism of Thermal Cruise Figure 7-11 Mechanism of Thermal Cruise W83627UHG TM mode. TM Mode (PWM Duty Cycle) TM ...
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... Output Value Mode mode. MART REGISTER NAME CPUTIN Temperature Sensor SYSTIN Temperature Sensor CPUFANOUT Output Value Select SYSFANOUT Output Value Select -44- W83627UHG TM mode. TM Mode Mode AN ATTRIBUTE BIT DATA 8 MSB, 1°C bit 7, Read only 0.5 °C Read only 8 MSB, 1°C 80h / FFh by ...
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... Bits 4-7 KEEP MIN. FAN TOLERANCE OUTPUT VALUE Bank0, Index 07h Bank0, Index 12h Bits 0-3 Bit5 Bank0, Index 07h Bank0, Index 12h Bits 4-7 Bit4 Pin 90 CPUFANOUT -45- W83627UHG TM Mode KEEP MIN. STEP- STOP STEP- FAN DOWN TIME UP TIME OUTPUT TIME VALUE ...
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... Bank0, Index 03h. In addition, the target temperature shifts to (Target Temperature + Temperature Tolerance), creating a new target temperature, named Target Temperature 1 in this figure. Setting Setting Setting Tolerance Tolerance Tolerance Tar. - Tol. Tar. - Tol. Tar. - Tol. Tar. + Tol. Tar. + Tol. Tar. + Tol. Figure 7-14 Setting of S MART -46- W83627UHG Temperature Temperature TM F III AN ...
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... Temperature Tolerance), creating a new target temperature named Target Temperature 1.This is illustrated in the figure below. Tolerance Tolerance Tar 1 Tar 1 Tar 3 Tar 3 Tar Tar Tar 2 Tar 2 Tar 4 Tar III Mechanism (Current Temp. > Target Temp. + Tol.) AN -47- W83627UHG Step Step Temperature Temperature Tar 5 Tar 5 Publication Release Date: May 25, 2007 Revision 1.0 ...
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... Tar 3 Tar 1 Tar III Mechanism (Current Temp. < Target Temp. – Tol.) AN MART REGISTER NAME CPUTIN Temperature Sensor CPUFANOUT Output Value Select -48- W83627UHG Temperature Temperature TM F III Mode AN ATTRIBUTE BIT DATA 8 MSB, 1°C bit 7, Read only 0.5 °C 80h / FFh by Bits 7-0 ...
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... Index 09h STEP DOWN STEP UP TIME TIME Bank0, Index Bank0, 0Fh Index 0Eh Fan Count limit * * * -49- W83627UHG III Control Mode MAX. FAN STOP OUTPUT TIME Bank0, Index Bank0, 67h Index 0Dh KEEP MIN. FAN OUTPUT VALUE Bank0, Index ...
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... Hysteresis) to 127°C. HYST . This is illustrated in the figure below HYST SMI# * Figure 7-18 SMI Mode of SYSTIN I (Temperature Hysteresis) lower than T HYST . Once the temperature rises above T HYST , until the temperature falls below T O -50- W83627UHG and setting Bank0 however This interrupt must be HYST ...
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... Hysteresis) lower than T HYST , however, and generates an interrupt, this mode does not *Interrupt Reset when Interrupt Status Registers are read Figure 7-19 SMI Mode of SYSTIN II -51- W83627UHG and setting Bank0 O , until the temperature O * Publication Release Date: May 25, 2007 Revision 1.0 . ...
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... The OVT# pin has two interrupt modes, comparator and interrupt. The modes are illustrated in this figure HYST SMI *Interrupt Reset when Interrupt Status Registers are read Figure 7-20 SMI Mode of CPUTIN . Once the temperature rises above T HYST , until the temperature falls below T O -52- W83627UHG * * * This interrupt must be HYST ...
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... To * *Interrupt Reset when Temperature sensor registers are read and has not yet fallen below Once the temperature rises above T HYST . This interrupt must be reset by reading all HYST -53- W83627UHG * * . The OVT# pin is HYST . HYST , however, and O Publication Release Date: May 25, 2007 Revision 1.0 ...
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... STATUS 7.7.4 BEEP Alarm Function The W83627UHG provides an alarm output function at the BEEP/GP21 pin. The BEEP/GP21 pin is a multi-function pin and can be configured as BEEP output, if Logical Device B, CR[F2h], bit 1 is set to zero. The BEEP outputs a warning tone when one of the monitored parameters in the following events is out of the preset range ...
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... Data Port (Port x6h) Attribute: Size: BIT 7 6 NAME DEFAULT 0 0 BIT 7-0 Data to be read from written to Value RAM and Register. Bit 6:0 Read/Write , Bit 7: Reserved 8 bits DATA DESCRIPTION 00h (Address Pointer) Read/Write 8 bits DATA DESCRIPTION -55- W83627UHG Publication Release Date: May 25, 2007 Revision 1 ...
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... The PWM duty cycle is equal to this 8-bit value, divided by 255, times 100%. FFh creates a duty cycle of 100%, and 00h creates a duty cycle of 0%. Strap by FAN_SET (Pin 119) SYSFANOUT voltage control. The output voltage is calculated equation: AVCC OUTPUT Voltage = Strap by FAN_SET (Pin 119) -56- W83627UHG Input Clock 1 ∗ Pre_Scale Divider ...
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... CPUFANOUT PWM Duty. The PWM duty cycle is equal to this 8-bit value, divided by 255, times 100%. FFh creates a duty cycle of 100%, and creates a duty cycle of 0%. Strap by FAN_SET (Pin 119) CPUFANOUT Voltage Control. The output voltage is calculated according to this equation: AVCC OUTPUT Voltage = Strap by FAN_SET (Pin 119) -57- W83627UHG ...
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... Index 05h (Bank 0) Attribute: Size: FUNCTION MODE TM Thermal Cruise DESCRIPTION DEFAULT Fan Speed DESCRIPTION TM Cruise DEFAULT Read/Write 8 bits SYSFAMOUT_MODE DESCRIPTION TM Mode. TM Mode III Mode. MART AN TM Mode. TM Mode. Read/Write 8 bits Reserved SYSTIN Target Temperature SYSFANIN Target Speed -58- W83627UHG 1 0 CPUFANOUT_SEL SYSFANOUT_SEL ...
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... CPUTIN Target Temperature / CPUFANIN Target Speed Reserved CPUTIN Target Temperature CPUFANIN Target Speed Read/Write 8 bits Tolerance of CPUTIN Target Temperature Tolerance of CPUFANIN Target Speed Read/Write 8 bits SYSFANOUT Stop Value -59- W83627UHG Tolerance of SYSTIN Target Temperature Tolerance of SYSFANIN Target Speed Publication Release Date: May 25, 2007 Revision 1 ...
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... CPUFANOUT value increases from zero to this eight-bit register value to provide a minimum value to turn on the fan. Read/Write 8 bits 5 4 CPUFANOUT Stop Value III mode, the CPUFANOUT value decreases to this eight- MART AN Read/Write 8 bits 5 4 SYSFANOUT Start-up Value 0 0 Read/Write 8 bits 5 4 CPUFANOUT Start-up Value 0 0 -60- W83627UHG ...
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... Fan Output Step Down Time Register - Index 0Eh (Bank 0) Attribute: Size: BIT 7 6 NAME DEFAULT 0 0 Read/Write 8 bits SYSFANOUT Stop Time Read/Write 8 bits CPUFANOUT Stop Time III mode, this register determines the amount of time it MART AN Read/Write 8 bits FANOUT Value Step Down Time -61- W83627UHG Publication Release Date: May 25, 2007 Revision 1 ...
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... SYSFANOUT_MIN_VALUE. 0: SYSFANOUT value decreases to zero when the temperature goes below the target range. 1: SYSFANOUT value decreases to the value specified in Index 08h when the temperature goes below the target range. Read/Write 8 bits FANOUT Value Step Up Time Read/Write 8 bits 5 CPUFANOUT_MIN_VALUE 0 DESCRIPTION -62- W83627UHG RESERVED ...
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... BIT 7 RESERVED. 6 DIS_OVT1. 0: Enable SYSTIN OVT# output. 1: Disable temperature sensor SYSTIN over-temperature (OVT#) output. 5 RESERVED. 4 OVT1_MODE. 0: Compare Mode. (Default) 1: Interrupt Mode. 3-0 RESERVED. DESCRIPTION Read/Write 8 bits 5 4 RESERVED OVT1_MODE 0 0 DESCRIPTION -63- W83627UHG RESERVED Publication Release Date: May 25, 2007 Revision 1.0 ...
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... AVCC Low Limit 31h 5VCC High Limit 32h 5VCC Low Limit 33h VIN1 High Limit 34h VIN1 Low Limit 35h VIN2 High Limit 36h VIN2 Low Limit 37h Reserved 38h Reserved 39h SYSTIN temperature sensor High Limit W83627UHG DESCRIPTION -64- ...
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... START. A one enables startup of monitoring operations. A zero puts the part in standby mode. Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "INT_Clear'' bit. DESCRIPTION RESERVED INT_CLEAR DESCRIPTION -65- W83627UHG 2 1 RESERVED SMI#ENABLE START 0 1 Publication Release Date: May 25, 2007 Revision 1 ...
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... RESERVED. 2 VIN2. A one indicates the high or low limit of VIN2 has been exceeded. 1 RESERVED. 0 VIN1. A one indicates the high or low limit of VIN1 has been exceeded CPUTIN SYSTIN 5VCC DESCRIPTION RESERVED CASEOPEN RESERVED DESCRIPTION -66- W83627UHG AVCC VIN0 CPUVCORE VIN2 RESERVED VIN1 mode. TM mode. ...
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... Interrupt Status Register 1 – Index 41h (Bank 0)). RESERVED CASEOPEN RESERVED DESCRIPTION A one disables the corresponding interrupt status bit for the SMI interrupt. (Please see Interrupt Status Register 2 – Index 42h (Bank 0)). Publication Release Date: May 25, 2007 -67- W83627UHG AVCC VIN0 CPUVCORE (PIN 97 VIN2 VIN1 Revision 1 ...
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... SYSFANIN DIV_B1 (SYSFANIN Divisor). 4 SYSFANIN DIV_B0 (SYSFANIN Divisor). 3-0 RESERVED. 8.38 Serial Bus Address Register - Index 48h (Bank 0) Attribute: Read/Write Size: 8 bits RESERVED DESCRIPTION SYFANIN SYSFANIN DIV_B1 DIV_B0 DESCRIPTION Please see Register – Index 5Dh (Bank 0). -68- W83627UHG RESERVED VBAT Monitor Control ...
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... Bits Select CPUTIN as CPUFANOUT Monitor Source. (Default Reserved Select PECI Agent 1 as CPUFANOUT monitor source Select PECI Agent 2 as CPUFANOUT monitor source Select PECI Agent 3 as CPUFANOUT monitor source Select PECI Agent 4 as CPUFANOUT monitor source. -69- W83627UHG CPUFANOUT CPUFANOUT TEMP_SEL[1] TEMP_SEL[0] 0 ...
Page 81
... Select SYSTIN as SYSFANOUT monitor source. (Default Select CPUTIN as SYSFANOUT monitor source Reserved Reserved Select PECI Agent 1 as SYSFANOUT monitor source Select PECI Agent 2 as SYSFANOUT monitor source Select PECI Agent 3 as SYSFANOUT monitor source Select PECI Agent 4 as SYSFANOUT monitor source ADCOVSEL -70- W83627UHG RESERVED RESERVED ...
Page 82
... Disable temperature sensor CPUTIN over-temperature (OVT) output. 0: Enable CPUTIN OVT output through pin OVT#. (Default) 2 OVTPOL (Over-temperature polarity). 1: OVT# is active high. 0: OVT# is active low. (Default) 1-0 RESERVED. DESCRIPTION EN_T1_ONE RESERVED DIS_OVT2 DESCRIPTION Publication Release Date: May 25, 2007 -71- W83627UHG OVTPOL RESERVED Revision 1.0 ...
Page 83
... RESERVED. This bit should not be set to zero. 2 BANKSEL2. Bank Select for Index Ports 0x50h~0x5Fh. The three-bit binary value 1 BANKSEL1. corresponds to the bank number. For example, “010” selects bank 2. 0 BANKSEL0 FANOPV2 DESCRIPTION RESERVED BANKSEL2 DESCRIPTION -72- W83627UHG FANINC2 FANOPV1 FANNC1 BANKSEL1 BANKSEL0 ...
Page 84
... Read Only 16 bits 13 12 VIDL VIDH 1 0 DESCRIPTION EN_ EN_ CPUTIN SYSTIN _BP _BP DESCRIPTION 1: Enable BEEP output. 0: Disable BEEP output. (Default) -73- W83627UHG EN_ EN_ EN_ 5VCC AVCC VIN0 CPUVCORE _BP _BP _BP Publication Release Date: May 25, 2007 Revision 1.0 ...
Page 85
... EN_VIN2_BP. BEEP output control for VIN2 if the monitored value exceeds the limit. 1: Enable BEEP output. 0: Disable BEEP output. (Default) 0 EN_VIN1_BP. BEEP output control for VIN1 if the monitored value exceeds the limit. 1: Enable BEEP output. 0: Disable BEEP output. (Default) DESCRIPTION EN_CASEOPEN_BP RESERVED DESCRIPTION -74- W83627UHG EN_VIN2_BP EN_VIN1_BP ...
Page 86
... SELPIIV1. Diode mode selection for temperature SYSTIN, if Index 5Dh, bit 1 is set CPU-compatible thermal diode. 0: Reserved. 3-0 RESERVED. 8.51 Reserved Register - Index 5Ah ~ 5Ch (Bank 0) 8.52 VBAT Monitor Control Register - Index 5Dh (Bank 0) Attribute: Read/Write Size: 8 bits CHIPID DESCRIPTION SELPIIV2 SELPIIV1 DESCRIPTION Publication Release Date: May 25, 2007 -75- W83627UHG RESERVED Revision 1.0 ...
Page 87
... Read/Write Size: 8 bits BIT EN_CPUFAN OUT NAME RESERVED CRITICAL TEMP DEFAULT SYSFANIN RESERVED DIV_B2 DESCRIPTION FAN DIVISOR BIT EN_SYSFANOUT RESERVED CRITICAL TEMP 0 0 -76- W83627UHG DIODES2 DIODES1 VBAT_MNT BIT 1 BIT 0 FAN DIVISOR 128 2 1 EN_CPUTIN EN_SYSTIN CURRENT CURRENT RESERVED MODE MODE EN_ ...
Page 88
... Reserved Registers - Index 64h (Bank 0) 8.60 Reserved Registers - Index 65h (Bank 0) 8.61 Reserved Registers - Index 66h (Bank 0) 8.62 CPUFANOUT Maximum Output Value Register - Index 67h (Bank 0) Attribute: Read/Write Size: 8 bits 7 6 BIT DESCRIPTION Publication Release Date: May 25, 2007 -77- W83627UHG Revision 1.0 ...
Page 89
... In Thermal Cruise mode, when SYSFANOUT critical temperature is enabled and monitor temperature over the critical temperature then SYSFANOUT will full drive. 8.67 CPUFANOUT Critical Temperature register - Index 6Ch (Bank 0) Attribute: Read/Write Size: 8 bits CPUFANOUT Max. Value CPUFANOUT STEP SYSFANOUT CRITICAL TEMPERATURE -78- W83627UHG ...
Page 90
... BIT 7 TEMP<0>. Temperature <0> of the CPUTIN/PECI sensor. The nine-bit value is in units of ° 0.5 C. 6-0 RESERVED. ( See CPUFANOUT monitor Temperature source select register – Index 49h(Bank CPUFANOUT CRITICAL TEMPERATURE TEMP<8:1> DESCRIPTION RESERVED DESCRIPTION Publication Release Date: May 25, 2007 -79- W83627UHG Revision 1.0 ...
Page 91
... THYST<8:1>. Hysteresis temperature bits 8-1. The nine-bit value is in units of 0.5 ° the default 8.74 CPUTIN Hysteresis (Low Byte) Register - Index 54h (Bank 1) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME THYST<0> DEFAULT FAULT RESERVED DESCRIPTION THYST<8:1> DESCRIPTION RESERVED -80- W83627UHG OVTMOD STOP ° C, and ...
Page 92
... TEMP<8:1>. Temperature <8:1> of the SYSTIN/CPUTIN/PECI sensor. The nine-bit value ° units of 0 See SYSFANOUT monitor Temperature source select register – Index 4Ah(Bank 0) ) DESCRIPTION TOVF<8:1> DESCRIPTION RESERVED DESCRIPTION TEMP<8:1> DESCRIPTION Publication Release Date: May 25, 2007 -81- W83627UHG ° ° C, and the ° Revision 1.0 ...
Page 93
... Read Only Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT BIT 7-2 RESERVED. 1 VBAT. A one indicates the high or low limit of VBAT has been exceeded. 0 5VSB. A one indicates the high or low limit of 5VSB has been exceeded RESERVED DESCRIPTION RESERVED DESCRIPTION -82- W83627UHG VBAT 5VSB ...
Page 94
... RESERVED DESCRIPTION A one disables the corresponding interrupt status bit for the SMI interrupt. (Please see Interrupt Status Register 3 – Index 50h (Bank 4)). EN_ RESERVED USER_BP DESCRIPTION Publication Release Date: May 25, 2007 -83- W83627UHG VBAT 5VSB EN_ EN_ VBAT_BP 5VSB_BP Revision 1.0 ...
Page 95
... Reserved Register - Index 57h-58h (Bank 4) 8.92 Real Time Hardware Status Register I - Index 59h (Bank 4) Attribute: Read Only Size: 8 bits BIT 7 6 CPUFANIN SYSFANIN NAME _STS _STS DEFAULT OFFSET<7:0> DESCRIPTION OFFSET<7:0> DESCRIPTION CPUTIN SYSTIN 5VCC _STS _STS _STS -84- W83627UHG AVCC VIN0 CPUVCORE _STS _STS _STS ...
Page 96
... CPUVCORE voltage is in the allowed range. 8.93 Real Time Hardware Status Register II - Index 5Ah (Bank 4) Attribute: Read Only Size: 8 bits BIT 7 6 NAME TAR2_STS TAR1_STS DEFAULT 0 0 DESCRIPTION 5 4 RESERVED CASEOPEN_STS 0 0 Publication Release Date: May 25, 2007 -85- W83627UHG RESERVED VIN1_STS Revision 1.0 ...
Page 97
... VBAT_STS. VBAT Voltage Status. 1: VBAT voltage is over or under the allowed range. 0: VBAT voltage is in the allowed range. 0 5VSB_STS. 5VSB Voltage Status. 1: 5VSB voltage is over or under the allowed range. 0: 5VSB voltage is in the allowed range. DESCRIPTION TM mode. TM mode VIN2_STS RESERVED DESCRIPTION -86- W83627UHG VBAT_STS 5VSB_STS ...
Page 98
... High Limit 55h 5VSB Low Limit 56h VBAT High Limit 57h VBAT Low Limit 58h Reserved 59h Reserved 5Ah Reserved 5Bh Reserved 5Ch Reserved 8.97 Reserved Register - Index 50h - 57h (Bank 6) W83627UHG DESCRIPTION Publication Release Date: May 25, 2007 -87- Revision 1.0 ...
Page 99
... FLOPPY DISK CONTROLLER 9.1 FDC Functional Description The floppy disk controller (FDC) of the W83627UHG integrates all of the logic required for floppy disk control. The FDC implements a FIFO, which provides better system performance in multi-master systems, and the digital data separator supports data rates bits/sec. ...
Page 100
... A single command puts the FDC into perpendicular mode. All other commands operate as they normally do. Perpendicular mode requires a 1 Mbps data rate for the FDC, and, at this data rate, the FIFO manages the host interface bottleneck due to the high speed of data transfer to and from the disk. W83627UHG Publication Release Date: May 25, 2007 -89- Revision 1.0 ...
Page 101
... FDC Core The W83627UHG FDC is capable of performing twenty commands. Each command is initiated by a multi-byte transfer from the microprocessor, and the result may be a multi-byte transfer back to the microprocessor. Each command consists of three phases: command, execution, and result. Command The microprocessor issues all required information to the controller to perform a specific operation. ...
Page 102
... C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ HDS DS1 DS0 -91- W83627UHG D0 REMARKS 1 0 Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Publication Release Date: May 25, 2007 Revision 1.0 ...
Page 103
... HDS DS1 DS0 HDS DS1 DS0 -92- W83627UHG D0 REMARKS 0 Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution D0 REMARKS 0 Command codes Sector ID information prior to command execution Data transfer between the FDD and system ...
Page 104
... HDS DS1 DS0 HDS DS1 DS0 -93- W83627UHG D0 REMARKS Status information after command execution Sector ID information after command execution D0 REMARKS 1 0 Command codes The first correct ID information on the cylinder is stored in the Data Register Status information after command execution Disk status after the ...
Page 105
... HDS DS1 DS0 -94- W83627UHG REMARKS D0 Status information after command execution Sector ID information after command execution D0 REMARKS 0 Command code 0 Enhanced controller D0 REMARKS 1 Command codes Sector ID information prior to Command execution Data transfer between the FDD and system Status information after Command execution Sector ID information after ...
Page 106
... HDS DS1 DS0 HDS DS1 DS0 -95- W83627UHG D0 REMARKS 1 Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution D0 REMARKS 1 Command codes Bytes per Sector Sectors per Cylinder ...
Page 107
... DS1 DS0 HDS DS1 DS0 -96- W83627UHG D0 REMARKS Status information after command execution D0 REMARKS 1 Command codes Head retracted to Track 0 Interrupt D0 REMARKS 0 Command code Status information at the end of each seek operation D0 REMARKS 1 Command codes D0 REMARKS 1 Command codes Head positioned over proper cylinder on diskette ...
Page 108
... Sense Drive Status HDS DS1 DS0 GAP GAP LOCK 0 0 -97- W83627UHG D0 REMARKS 1 Configure information 0 Internal registers written D0 REMARKS 1 Command codes D0 REMARKS 1 0 Registers placed in FIFO WG D0 REMARKS 0 Command Code D0 REMARKS 0 Command Code 0 0 Publication Release Date: May 25, 2007 Revision 1.0 ...
Page 109
... Invalid Codes ----------------- Result R -------------------- ST0 ---------------------- 9.3 Register Descriptions There are several status, data, and control registers in the W83627UHG. These registers are defined below, and the rest of this section provides more detail about each one of them. ADDRESS OFFSET base address + 0 base address + 1 ...
Page 110
... INDEX. Indicates the complement of the INDEX# output. 1 WP. 0: The disk is not write-protected. 1: The disk is write-protected. 0 DIR#. Indicates the direction of the head movement. 0: Inward direction. 1: Outward direction. DESCRIPTION STEP F/F TRAK0 HEAD DESCRIPTION Publication Release Date: May 25, 2007 -99- W83627UHG INDEX WP DIR Revision 1.0 ...
Page 111
... WD# output pin. 3 RDATA F/F. Indicates the complement of the latched RDATA# output pin F/F. Indicates the complement of the latched WE# output pin. 1-0 Reserved Drive WDTA RDTA SEL0 Toggle Toggle DESCRIPTION RDATA DSA# WD F/F F DESCRIPTION -100- W83627UHG MOT EN MOT F/F DSD# DSC ...
Page 112
... Tape sel 0. If the three-mode FDD function is enabled (EN3MODE = 1 in LD0 CRF0, Bit 0), the bit definitions are as follows MOTOR DMA&INT ENABLE A ENABLE DESCRIPTION RESERVED DESCRIPTION Publication Release Date: May 25, 2007 -101- W83627UHG FDC DRIVE SELECT RESET Tape sel 1 Tape sel Revision 1.0 ...
Page 113
... Assign a logical drive number to the tape drive. Drive 0 is not available as a tape drive and is reserved for the floppy disk boot drive. TAPE SEL Non-DMA FDD 3 FDC Busy mode Busy -102- W83627UHG Floppy Tape Sel Tape Sel Boot 1 0 Drive DRIVE SELECTED None ...
Page 114
... PRECOMP 1. 2 PRECOMP 0. DESCRIPTION PRECOMP2 PRECOMP1 DESCRIPTION Selects the value of write precompensation. The following precompensation combination of these bits. Please see the tables below. Publication Release Date: May 25, 2007 -103- W83627UHG PRECOMP0 DRATE1 DRATE0 tables show the values for every Revision 1.0 ...
Page 115
... MB/S (MFM), Illegal (FM), RWC PRECOMPENSATION DELAY 250K - 1 Mbps Default Delays 41.67 ns 83.34 ns 125.00 ns 166.67 ns 208.33 ns 250.00 ns 0.00 ns (disabled) DEFAULT PRECOMPENSATION DELAYS 125 ns 125 ns 125 ns 41.67ns 20.8 ns -104- W83627UHG 2 Mbps Tape drive Default Delays 20.8 ns 41.17 ns 62.5ns 83.3 ns 104.2 ns 125.00 ns 0.00 ns (disabled) ...
Page 116
... The FIFO register stores data, commands, and parameters, and it provides disk- drive status information. In addition, data bytes pass through the data register to program or obtain results after a command. In the W83627UHG, this register is disabled after reset. The FIFO can enable it and change its values through the configure command. ...
Page 117
... If the FDC detects a CRC error in the data field error (Wrong Cylinder). 1: Indicates wrong cylinder (Scan Equal Hit). 1: During execution of the Scan command, if the equal condition is satisfied error (Scan Not Satisfied). 1: During execution of the Scan command error Not Used DESCRIPTION DESCRIPTION -106- W83627UHG MAM ...
Page 118
... The bit definitions are as follows: BIT 7 6 NAME DSKCHG DEFAULT 0 NA BIT 7 DSKCHG. 6-0 RESERVED. Reserved for the hard disk controller. During a read of this register, these bits are in tri-state. DESCRIPTION DESCRIPTION RESERVED DESCRIPTION Publication Release Date: May 25, 2007 -107- W83627UHG US1 US0 Revision 1.0 ...
Page 119
... DMAEN NOPREC DESCRIPTION Select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR Register) (Write base address +4)) for how the settings correspond to individual data rates. -108- W83627UHG HIGH DRATE0 DENS DRATE1 DRATE0 0 1 ...
Page 120
... RESERVED DESCRIPTION Select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR Register) (Write base address + 4)) for how the settings correspond to individual data rates. Publication Release Date: May 25, 2007 -109- W83627UHG DRATE1 DRATE0 NOPREC DRATE1 DRATE0 0 ...
Page 121
... PBE (Parity Bit Enable). When this bit is set to logic 1, the transmitter inserts a stop bit between the last data bit and the stop bit of the SOUT, and the receiver checks the parity bit in the same position PBFE EPE PBE DESCRIPTION -110- W83627UHG MSBE DLS1 DLS0 ...
Page 122
... DLS0 (Data Length Select Bit 0). Defines the number of data bits that are sent or checked in each serial character. DLS1 The following table identifies the remaining UART registers. Each one is described separately in the following sections. DESCRIPTION DLS0 Publication Release Date: May 25, 2007 -111- W83627UHG DATA LENGTH 5 bits 6 bits 7 bits 8 bits Revision 1.0 ...
Page 123
... CTS DSR RI Falling Toggling Toggling Edge (TCTS) (TDSR) (FERI) Bit 0 Bit 1 Bit 2 Bit 0 Bit 1 Bit 2 Bit 8 Bit 9 Bit 10 -112- W83627UHG Data RX Data RX Data Bit 3 Bit 4 Bit 5 TX Data TX Data TX Data Bit 3 Bit 4 Bit 5 HSR 0 0 Interrupt Enable (EHSRI) ...
Page 124
... RDR (RBR Data Ready). This bit is set to logical 1 to indicate that the received data are ready to be read by the CPU in the RBR or FIFO. When no data are left in the RBR or FIFO, the bit is set to logical TBRE SBD NSER DESCRIPTION Publication Release Date: May 25, 2007 -113- W83627UHG PBER OER PDR Revision 1.0 ...
Page 125
... This register reflects the current state of four input pins used with handshake peripherals such as modems and records changes on these pins BIT NAME DCD DEFAULT INTERNAL IRQ LOOPBACK ENABLE ENABLE DESCRIPTION DSR CTS TDCD -114- W83627UHG LOOPBACK RTS DTR RI INPUT FERI TDSR TCTS ...
Page 126
... NA 0 DESCRIPTION These two bits are used to set the active level of the receiver FIFO interrupt. The active level is the number of bytes that must be in the receiver FIFO to generate an interrupt. Publication Release Date: May 25, 2007 -115- W83627UHG RECEIVER FIFO FIFO ENABLE RESET 0 ...
Page 127
... INTERRUPT SET AND FUNCTION Interrupt Type Interrupt Source - No Interrupt pending UART Receive 1. OER = 1 Status 3. NSER = 1 4. SBD = 1 RBR Data Ready 1. RBR data ready 2. FIFO interrupt active level reached -116- W83627UHG INTERRUPT INTERRUPT STATUS STATUS INTERRUPT BIT 1 BIT ...
Page 128
... Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. TBR Empty TBR empty Handshake status 1. TCTS = 1 3. FERI = EHSRI 0 0 DESCRIPTION -117- W83627UHG Clear Interrupt Read RBR 1. Write data into TBR 2. Read ISR (if priority is third) 2. TDSR = 1 Read HSR 4. TDCD = EUSRI ETBREI 0 ...
Page 129
... PARALLEL PORT 11.1 Printer Interface Logic The W83627UHG parallel port can be attached to devices that accept eight bits of parallel data at standard TTL level. The W83627UHG supports the IBM XT/AT compatible parallel port (SPP), the bi- directional parallel port (BPP), the Enhanced Parallel Port (EPP), and the Extended Capabilities Parallel Port (ECP) ...
Page 130
... PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 SLCT ERROR -119- W83627UHG PD2 PD1 1 1 TMOUT INIT# AUTOFD# STROBE# INIT# AUTOFD# STROBE# PD2 PD1 PD2 PD1 PD2 PD1 PD2 PD1 PD2 PD1 3 ...
Page 131
... AUTO FD. A logical 1 causes the printer to line-feed after a line is printed. STROBE. A logical 1 generates an active-high pulse for a minimum of 0.5 μs to clock 0 data into the printer. Valid data must be presented for a minimum of 0.5 μs before and after the strobe pulse. DESCRIPTION DIR IRQ ENABLE SLCT DESCRIPTION -120- W83627UHG INIT# AUTO FD STROBE ...
Page 132
... During a read operation, ports PD0-PD7 are read, and the leading edge of IOR# causes an EPP read cycle to be performed and the data to be output to the host CPU PD5 PD4 PD3 PD5 PD4 PD3 Publication Release Date: May 25, 2007 -121- W83627UHG PD2 PD1 PD0 PD2 PD1 PD0 Revision 1.0 ...
Page 133
... If nWait is inactive high, the read/write cycle cannot start. It must wait until nWait changes to active low, at which time it starts is as described above. W83627UHG EPP DESCRIPTION -122- ...
Page 134
... Extended Capabilities Parallel (ECP) Port This port is software- and hardware-compatible with existing parallel ports, so the W83627UHG parallel port may be used in standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward (host-to-peripheral) and reverse (peripheral-to-host) directions ...
Page 135
... PD4 PD3 PError Select nFault Directio ackIntEn SelectIn nErrIntrEn dmaEn -124- W83627UHG FUNCTION Data Register ECP FIFO (Address) Status Register Control Register Parallel Port Data FIFO ECP FIFO (DATA) Test FIFO Configuration Register A Configuration Register B Extended Control Register NOTE PD2 PD1 ...
Page 136
... Device Control Register (DCR) The bit definitions are as follows: BIT 7 6 NAME DEFAULT PD5 PD4 PD3 Address or RLE PError Select nFault DESCRIPTION Director ackInEn SelectIn -125- W83627UHG 2 1 PD2 PD1 PD0 nInit Autofd Strobe NA NA Publication Release Date: May 25, 2007 Revision 1 ...
Page 137
... However, data in the tFIFO may be displayed on the parallel port data lines. 11.3.8 CNFGA (Configuration Register A) Mode = 111 This register is a read-only register. When it is read, 10H is returned. This indicates that this is an 8-bit implementation. W83627UHG DESCRIPTION -126- ...
Page 138
... NAME MODE MODE DEFAULT IRQx2 IRQx1 DESCRIPTION IRQ resource Reflects other IRQ resources selected by PnP register (default) IRQ7 IRQ9 IRQ10 IRQ11 IRQ14 IRQ15 IRQ5 5 4 MODE nErrIntrEn dmaEn 0 1 -127- W83627UHG IRQx0 ServiceIntr Full Publication Release Date: May 25, 2007 Revision 1 Empty 1 ...
Page 139
... FIFO. (c) dmaEn = 0, direction = 1: This bit is set to logical 1 whenever there are readIntr threshold or more valid bytes to be read from the FIFO. 1: Disable DMA and all of the service interrupts. Writing a logical 1 to this bit does not cause an interrupt. W83627UHG DESCRIPTION -128- ...
Page 140
... ECP mode. This signal sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. This signal is always deasserted in ECP mode. -129- W83627UHG The host relies Publication Release Date: May 25, 2007 Revision 1.0 upon ...
Page 141
... PeriphAck is low. The most significant bit of the command is always zero. 11.3.12.3 Data Compression The W83627UHG hardware supports RLE decompression and can transfer compressed data to a peripheral. Odd (RLE) compression is not supported in the hardware, however. In order to transfer data in ECP mode, the compression count is written to ecpAFifo and the data byte is written to ecpDFifo ...
Page 142
... The host must set dmaEn and serviceIntr to 0 and also must set the direction and state accordingly in the programmed I/O transfers. The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The programmed I/O empties or fills the FIFO using the appropriate direction and mode. W83627UHG Publication Release Date: May 25, 2007 -131- Revision 1.0 ...
Page 143
... KEYBOARD CONTROLLER The W83627UHG KBC (8042 with licensed KB BIOS) circuit is designed to provide the functions needed to interface a CPU with a keyboard and/or a PS/2 mouse and can be used with IBM compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer ...
Page 144
... It defaults to 0 after a power-on reset. 0: Data byte 1: Command byte 0: Keyboard is inhibited 1: Keyboard is not inhibited 0: Auxiliary device output buffer empty 1: Auxiliary device output buffer full 0: No time-out error 1: Time-out error 0: Odd parity 1: Even parity (error) -133- W83627UHG Publication Release Date: May 25, 2007 Revision 1.0 ...
Page 145
... System Flag 2 1 Enable Auxiliary Interrupt 0 Enable Keyboard Interrupt BIT BIT DEFINITION No Error Detected 00 01 Auxiliary Device "Clock" line is stuck low Auxiliary Device "Clock" line is stuck high 02 03 Auxiliary Device "Data" line is stuck low 04 Auxiliary Device "Data" line is stuck low -134- W83627UHG ...
Page 146
... BIT DEFINITION BIT No Error Detected 00 01 Keyboard "Clock" line is stuck low 02 Keyboard "Clock" line is stuck high Keyboard "Data" line is stuck low 03 04 Keyboard "Data" line is stuck high 5 4 RESERVED 0 0 -135- W83627UHG P92EN HGA20 Publication Release Date: May 25, 2007 Revision 1.0 0 HKBRST 0 ...
Page 147
... KBRESET is pulse low for 6 μs (Min.) with a 14 μs (Min.) delay. GATE A20 and KBRESET are controlled by either software or hardware logic, and they are mutually exclusive. Then, GATE A20 and KBRESET are merged with Port92 when the P92EN bit is set. W83627UHG DESCRIPTION Select the KBC clock rate. ...
Page 148
... PLKBRST (Pulled-low KBRESET). A logical 1 on this bit causes KBRESET to drive low for 6 μS(Min.) with a 14 μS(Min.) delay. Before issuing another keyboard-reset command, the bit must be cleared RES. (1) RES. ( DESCRIPTION Publication Release Date: May 25, 2007 -137- W83627UHG RES. (1) SGA20 PLKBRST Revision 1.0 ...
Page 149
... Logical Device A, CR[F2h], bit[0] and is for enabling or disabling the PME function. If this bit is set to “0”, the W83627UHG won’t output any PME signal when any of the wake-up events has occurred and is enabled. The four registers are divided into PME status registers and PME ...
Page 150
... PSOUT# PSOUT# PSOUT# PSOUT# PWRBTN# PWRBTN# PWRBTN# PWRBTN# South Bridge South Bridge South Bridge South Bridge Figure 13-1 Power Control Mechanism S0 State S5 State -139- W83627UHG PSON# PSON# PSON# PSON# VCC ON VCC ON VCC ON VCC ON VCC ON VCC ON Power Power Power Power Supply Supply ...
Page 151
... AC Power Failure Resume By definition, AC power failure means that the standby power is removed. The power failure resume control logic of the W83627UHG is used to recover the system to a pre-defined state after AC power failure. Two control bits at Logical Device A, CR[E4h], bits[6:5] indicate the pre-defined state. The ...
Page 152
... To ensure that VCC does not fall faster than VSB in various ATX Power Supplies, the W83627UHG adds the option of “user define mode” for the pre-defined state before AC power failure. BIOS can set the pre-defined state to be “On” or “Off”. According to this setting, the system is returned to the pre- defined state after the AC power recovery ...
Page 153
... The RSMRST# (Pin 75) signal is a reset output and is used as the 5VSB power on reset signal for the South Bridge. When the W83627UHG detects the 5VSB voltage rises to “V1”, it then starts a delay – “t1” before the rising edge of RSMRST# asserting. If the 5VSB voltage falls below “V2”, the RSMRST# de-asserts immediately ...
Page 154
... The PWROK (Pin 71) signal is an output and is used as both the 5VCC and 3VCC power-on reset signal. When the W83627UHG detects both of the 5VCC and 3VCC voltages rise to “V3” and “V5”, it then starts a delay – “t2” before the rising edge of PWROK assertion. If both of the 5VCC and 3VCC voltages fall below “ ...
Page 155
... Originally, the t2 timing is between 300 mS to 500 mS, but it can be changed to 200 mS to 300 mS by programming Logical Device A, CR[E6h], bit 3 to “1”. Furthermore, the W83627UHG provides four different extra delay time of PWROK for various demands. The four extra delay time are designed at Logical Device A, CR[E6h], bits 2~1 ...
Page 156
... SL=Slave Control Note: 1. The Start Frame pulse can be 4-8 clocks wide. 2. The first clock of Start Frame is driven low by the W83627UHG because IRQ1 of the W83627UHG needs an interrupt request. Then the host takes over and continues to pull the SERIRQ low. IRQ0 FRAME START FRAME ...
Page 157
... IRQ/Data Frame Once the Start Frame has been initiated, the W83627UHG must start counting frames based on the rising edge of the start pulse. Each IRQ/Data Frame has three clocks: the Sample phase, the Recovery phase, and the Turn-around phase. During the Sample phase, the W83627UHG drives SERIRQ low if the corresponding IRQ is active. If the corresponding IRQ is inactive, then SERIRQ must be left tri-stated ...
Page 158
... The Start Frame pulse of next SERIRQ cycle may or may not start immediately after the turn-around clock of the Stop Frame. IRQ15 IOCHCK# FRAME FRAME IRQ15 None T=Turn-around -147- W83627UHG STOP FRAME NEXT CYCLE STOP START Host Controller S=Sample I= Idle. Publication Release Date: May 25, 2007 Revision 1.0 2 ...
Page 159
... The W83627UHG outputs a low signal to the WDTO# pin (pin 77) when a time-out event occurs. In other words, when the value is counted down to zero, the timer stops, and the W83627UHG sets the WDTO# status bit in Logical Device 8, CR[F7h], bit[4], outputting a low signal to the WDTO# pin(pin 77) ...
Page 160
... GENERAL PURPOSE I/O 16.1 GPIO Architecture The W83627UHG provides 45 input/output ports that can be individually configured to perform a simple basic I/O function or an alternative, pre-defined function. GPIO ports 1 ~2 are configured through control registers in Logical Device 9, GPIO ports 3~4 in Logical Device 7, and GPIO ports 5~6 in Logic Device 8 ...
Page 161
... ADDRESS ABBR 7 GSR Base + 0 IOR Base + 1 DAT Base + 2 INV Base + 3 DST Base + 4 Table 16-2 GPIO Register Addresses BIT NUMBER Reserved GPIO I/O Register GPIO Data Register GPIO Inversion Register GPIO Status Register -150- W83627UHG INDEX ...
Page 162
... UARTF Power Down 0: Powered down 1: Not powered down UARTE Power Down 0: Powered down 1: Not powered down UARTD Power Down. 0: Powered down 1: Not powered down W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 0: Powered down 1: Not powered down 0: Powered down 1: Not powered down 0: Powered down 1: Not powered down ...
Page 163
... This bit is set or reset by a power-on strapping pin (Pin 52, DTRA#). Note 1 0 Reserved. Note1: Disable FDC interface Pin 5 CTSF# Pin 6 GP64 Pin 7 DSRF# Pin 8 RTSF# W83627UHG DESCRIPTION s: value by strapping DESCRIPTION Enable FDC interface Pin 5 DRVDEN0 Pin 6 INDEX# Pin 7 MOA# Pin 8 DSA# -152- ...
Page 164
... Reserved. HEFRAS => Write 87h to location 2E twice Write 87h to location 4E twice. The corresponding power-on strapping pin is RTSA# (Pin 51). LOCKREG => Enable R/W configuration registers Disable R/W configuration registers. W83627UHG Enable FDC interface Pin 9 DIR# Pin 10 STEP# Pin 11 WD# Pin 13 WE# Pin 14 TRAK0# Pin 15 ...
Page 165
... Enable UART E legacy mode for IRQ selection. Then HCR register 6 R/W (base address + 4) bit 3 is not effective when selecting IRQ Disable UART E legacy mode for IRQ selection. Then HCR register (base address + 4) bit 3 is not effective when selecting IRQ. W83627UHG DESCRIPTION DESCRIPTION -154- ...
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... 01: Power LED pin is driven low. 10: Power LED pin outputs 1Hz pulse with 50% duty cycle. 11: Power LED pin outputs 0 Reserved. DESCRIPTION Parallel Port Mode. Reserved. DESCRIPTION OVT# SMI pulse with 50% duty cycle. 4 -155- W83627UHG Publication Release Date: May 25, 2007 Revision 1.0 ...
Page 167
... DESCRIPTION 2 C interface) GP25, GP26 (Default) SDA, SCL DESCRIPTION Bit-1 Bit-0 Pin 82 Reserved 0 0 Pin 83 Reserved Others Pin 82 IRRX 0 1 Pin 83 IRTX Others 1 0 Pins Pins -156- W83627UHG (VSB Power) (VSB Power) Pins function ( tri-state) ( always low) GPIO1 GPIO1 GPIO1 UART B ...
Page 168
... Reserved. 0: Logical device is inactive Logical device is active. CR 60h, 61h. (Default 03h,F0h) BIT READ / WRITE These two registers select FDC I/O base address <100h : FF8h> 7 byte boundary. W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: May 25, 2007 -157- Revision 1.0 ...
Page 169
... Interface Mode. 3 FDC DMA Mode Floppy Mode DESCRIPTION DESCRIPTION 001: DMA1. 010: DMA2. DESCRIPTION 1: Drive and Motor select 0 and 1 are swapped. 00: Model 30. 10: Reserved. 0: Burst Mode is enabled 1: Non-Burst Mode. 0: Normal Floppy Mode. 1: Enhanced 3-mode FDD. -158- W83627UHG 011: DMA3. 01: PS/2. 11: AT Mode ...
Page 170
... Reserved. Data Rate Table selection (Refer to TABLE A). 4 00: Select regular drives and 2.88 format. 01: 3-mode drive. 2 Reserved. 1 Drive Type selection (Refer to TABLE B). W83627UHG DESCRIPTION 00: FDD A. 01: FDD B. 10: FDD C. 11: FDD D. 01 Normal. 11: 0 (Forced to logic 0). DESCRIPTION DESCRIPTION 10: 2 Meg Tape. ...
Page 171
... DRVDEN1 (pin 3) SELDEN DRATE0 DRATE1 DRATE0 DRATE0 SELDEN DRATE0 DRATE1 -160- W83627UHG SELDEN FM --- 1 250K 1 150K 0 125K 0 --- 1 250K 1 250K 0 125K 0 --- 1 250K 1 --- 0 125K 0 DRIVE TYPE 4/2/1 MB 3.5”“ ...
Page 172
... ECP and EPP – 1.9 mode. 100: Printer Mode. 101: EPP – 1.7 and SPP mode. 110: Reserved. 111: ECP and EPP – 1.7 mode. DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 001: DMA1. 010: DMA2. DESCRIPTION Publication Release Date: May 25, 2007 -161- W83627UHG 011: DMA3. Revision 1.0 ...
Page 173
... Using new RX FIFO Error Indication signal to solve some issues. 4~2 Reserved. 00: UART A clock source is 1.8462 MHz (24 MHz / 13). 01: UART A clock source is 2 MHz (24 MHz / 12). 1 00: UART A clock source is 24 MHz (24 MHz / 1). 00: UART A clock source is 14.769 MHz (24 MHz / 1.625). W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION -162- ...
Page 174
... RX mode to TX mode. 00: UART B clock source is 1.8462 MHz (24 MHz / 13). 01: UART B clock source is 2 MHz (24 MHz / 12). 1 00: UART B clock source is 24 MHz (24 MHz / 1). 00: UART B clock source is 14.769 MHz (24 MHz / 1.625). W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: May 25, 2007 -163- ...
Page 175
... Active pulse 3/16 bit time Inverting IRTX/SOUTB pin Inverting IRTX/SOUTB & 500 KHZ clock Inverting IRTX/SOUTB Inverting IRTX/SOUTB & 500 KHZ clock -164- W83627UHG IRRX High Demodulation into SINB/IRRX Demodulation into SINB/IRRX Routed to SINB/IRRX Routed to SINB/IRRX Demodulation into SINB/IRRX Demodulation into SINB/IRRX ...
Page 176
... These bits select IRQ resource for MINT. (PS/2 Mouse interrupt) CR F0h. (Default 83h) BIT READ / WRITE KBC clock rate selection 00: 6MHz 7 01: 8MHz 10: 12MHz 11: 16MHz 5~3 Reserved. W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: May 25, 2007 -165- Revision 1.0 ...
Page 177
... CR F0h. (Default 83h), continued BIT READ / WRITE 0: Port 92 disabled Port 92 enabled. 0: Gate A20 software control Gate A20 hardware speed up. 0: KBRST software control KBRST hardware speeds up. W83627UHG DESCRIPTION -166- ...
Page 178
... Reserved. 00: UART C clock source is 1.8462 MHz (24 MHz / 13). 01: UART C clock source is 2 MHz (24 MHz / 12). 1 00: UART C clock source is 24 MHz (24 MHz / 1). 00: UART C clock source is 14.769 MHz (24 MHz / 1.625). W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: May 25, 2007 -167- Revision 1.0 ...
Page 179
... CR E3h. (Status Register; Default 00h) BIT READ / WRITE GPIO3 Event Status Bit 7-0 corresponds to GP37-GP30, respectively. Read Only 7 active edge(rising/falling) has been detected Read-Clear active edge(rising/falling) has been detected Reading the status bit clears W83627UHG DESCRIPTION 1: GPIO4 is active. 1: GPIO3 is active. DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION -168- ...
Page 180
... READ / WRITE GPIO4 Event Status Bits 7-0 correspond to GP47-GP40, respectively. Read Only 7 active edge(rising/falling) has been detected Read-Clear active edge(rising/falling) has been detected Reading the status bit clears W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: May 25, 2007 -169- Revision 1.0 ...
Page 181
... BIT READ / WRITE GPIO5 Inversion register 0: The respective bit and the port value are the same. 7 The respective bit and the port value are inverted. (Both Input & Output ports) W83627UHG DESCRIPTION 1: GPIO6 is active. 1: GPIO5 is active. DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION -170- ...
Page 182
... READ / WRITE GPIO6 Event Status Bits 7-0 correspond to GP67-GP60, respectively. Read Only 7 active edge(rising/falling) has been detected Read-Clear active edge(rising/falling) has been detected Reading the status bit clears W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: May 25, 2007 -171- Revision 1.0 ...
Page 183
... Watch Dog Counter instead of Watch Dog Timer Time-out value. 7 00h: Time-out Disable 01h: Time-out occurs after 1 second/minute 02h: Time-out occurs after 2 second/minutes 03h: Time-out occurs after 3 second/minutes ………………………....................................... FFh: Time-out occurs after 255 second/minutes W83627UHG DESCRIPTION DESCRIPTION -172- ...
Page 184
... Trigger WDTO# event. This bit is self-clearing. WDTO# status bit Watchdog timer is running. Write “0” Clear 1: Watchdog timer issues time-out event. 3 These bits select IRQ resource for WDTO#. (02h for SMI# event.) W83627UHG DESCRIPTION Publication Release Date: May 25, 2007 -173- Revision 1.0 ...
Page 185
... CR E3h. (Status Register; Default 00h) BIT READ / WRITE GPIO1 Event Status Bits 7-0 correspond to GP17-GP10, respectively. Read Only 7 active edge(rising/falling) has been detected Read-Clear active edge(rising/falling) has been detected Reading the status bit clears W83627UHG DESCRIPTION 1: GPIO2 is active. 1: GPIO1 is active. DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION -174- ...
Page 186
... READ / WRITE Select Suspend LED mode. 00: Suspend LED pin is driven low. 7 01: Suspend LED pin is tri-stated. 10: Suspend LED pin outputs 1Hz pulse with 50% duty cycle. 11: Suspend LED pin outputs 5~0 Reserved. W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION pulse with 50% duty cycle. 4 ...
Page 187
... ENMDAT_UP MSRKEY DESCRIPTION DESCRIPTION DESCRIPTION MSXKEY -176- W83627UHG Wake-up event Any button clicked or movement. One click of either left or right MS button. One click of the MS left button. One click of the MS right button. Two clicks of the MS left button. Two clicks of the MS right button. ...
Page 188
... It is the data register of the keyboard pre-determined key combination characters, which is indexed by CRE1. CR E3h. (Event Status Register; Default 08h) BIT READ / WRITE 7~6 Reserved. Read Only 5 This event status is caused by VSB power off/on. Read-Clear W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: May 25, 2007 -177- Revision 1.0 ...
Page 189
... Password or sequence hot keys programmed in the registers. 1: Any key. Enable the hunting mode for all wake-up events set in CRE0. This bit is cleared when any wake-up events is captured. (LRESET Disable. 1: Enable. 1~0 Reserved. DESCRIPTION DESCRIPTION depending on the state before the power loss. CRE6[4]) -178- W83627UHG ...
Page 190
... Write 1 to this bit will clear CASEOPEN status. This bit will clear the status itself. The function is the same as Index 46h bit 7 of H/W Monitor part. Power-loss Last State Flag. (VBAT OFF. W83627UHG DESCRIPTION DESCRIPTION Publication Release Date: May 25, 2007 -179- Revision 1.0 ...
Page 191
... CRE4[6:5], logic device A. (for SiS & VIA chipsets) 0: Disable. 1: Enable. Select WDTO# reset source (VSB Watchdog timer is reset by LRESET#. 1: Watchdog timer is reset by PWROK. 2~1 Reserved. Hardware Monitor RESET source select (VBAT PWROK. 1: LRESET#. W83627UHG DESCRIPTION 01: Delay 32 ms 11: Delay 250 ms DESCRIPTION -180- ...
Page 192
... Write 1 to clear this status. PME status of the URE IRQ event W-Clear Write 1 to clear this status. PME status of the HM IRQ event W-Clear Write 1 to clear this status. DESCRIPTION 0: Disable PME. 1: Enable PME. DESCRIPTION DESCRIPTION Publication Release Date: May 25, 2007 -181- W83627UHG Revision 1.0 ...
Page 193
... Disable PME interrupt of the URF IRQ event Enable PME interrupt of the URF IRQ event. 0: Disable PME interrupt of the URE IRQ event Enable PME interrupt of the URE IRQ event. 0: Disable PME interrupt of the HM IRQ event Enable PME interrupt of the HM IRQ event. W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION -182- ...
Page 194
... Disable GP27 event route to PME Enable GP27 event route to PME#. 0: Disable GP26 event route to PME Enable GP26 event route to PME#. 0: Disable GP25 event route to PME Enable GP25 event route to PME#. W83627UHG DESCRIPTION DESCRIPTION Publication Release Date: May 25, 2007 -183- Revision 1.0 ...
Page 195
... This bit is strapped by pin 122 (SOUTD / GP42). 1 Read Only 0: PIN 107,108 1: PIN 107,108 FAN_SET strapping status. This bit is strapped by pin 119 (RTSD# / GP45). 0 Read Only 0: The initial speed is 100%. 1: The initial speed is 50%. DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION BEEP, PLED GP20, GP21 -184- W83627UHG ...
Page 196
... Agent 1 always returns the relative temperature from domain 1. (When CR E8 [3] is set to 1, this register is used to read the relative temperature of Agent 1 (Low Byte)). Note. Agent 1 ~ Agent 4 represent the addresses of PECI devices from 0x30h to 0x33h respectively. W83627UHG DESCRIPTION Publication Release Date: May 25, 2007 -185- Revision 1.0 ...
Page 197
... CR E8 [3] is set to 1, this register is used to read the relative temperature of Agent 3 (Low Byte)) Note1: TBase is a temperature reference based on the experiment of the processor actual temperature. For more details, please refer to section 7.5. W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION ...
Page 198
... Before reading this register, this must be set E8[3] CR E7h. (Agent 4 Relative Temperature (High Byte)) BIT READ / WRITE 7~0 Read Only Agent 4 Relative Temperature (High Byte) Before reading this register, this must be set E8[3] W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: May 25, 2007 -187- Revision 1.0 ...
Page 199
... Agt1RelTemp (Low Byte (High Byte) Agt2RelTemp (Low Byte (High Byte) Agt3RelTemp (Low Byte (High Byte Agt4RelTemp (Low Byte (High Byte) Agent 4 Absent Bit bit 7 Agent 3 Absent Bit bit 6 Agent 2 Absent Bit bit 5 Agent 1 Absent Bit bit 4 2 Reserved. W83627UHG DESCRIPTION -188- ...
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... Agent 3 TBase Register Agent 4 TBase Register PECI Domain Register Reserved Reserved Agent Alert Bit DESCRIPTION DESCRIPTION -189- W83627UHG CR E8 BIT Agt1RelTemp (Low Byte) Agt1RelTemp (High Byte) Agt2RelTemp (Low Byte) Agt2RelTemp (High Byte) Agt3RelTemp (Low Byte) Agt3RelTemp (High Byte) Agt4RelTemp (Low Byte) ...