W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 139

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BIT
7-5
4
3
2
Mode. Read/Write. These bits select the mode.
nErrIntrEn. Read/Write (Valid only in ECP Mode)
0: Enables the interrupt generated on the falling edge of nFault. This prevents interrupts
from being lost in the time between the read of the ECR and the write of the ECR.
1: Disables the interrupt generated on the asserting edge of nFault.
dmaEn. Read/Write.
0: Disable DMA unconditionally.
1: Enable DMA.
serviceIntr. Read/Write.
0: Enable one of the following cases of interrupts. When one of the serviced interrupts
(a) dmaEn = 1: During DMA, this bit is set to logical 1 when terminal count is reached.
(b) dmaEn = 0, direction = 0: This bit is set to logical 1 whenever there are writeIntr
(c) dmaEn = 0, direction = 1: This bit is set to logical 1 whenever there are readIntr
1: Disable DMA and all of the service interrupts. Writing a logical 1 to this bit does not
cause an interrupt.
000
001
010
011
100
101
110
111
occurs, this bit is set to logical 1 by the hardware. This bit must be reset to logical 0 to
re-enable the interrupts.
threshold or more bytes free in the FIFO.
threshold or more valid bytes to be read from the FIFO.
Standard Parallel Port (SPP) mode. The FIFO is reset in this mode.
PS/2 Parallel Port mode. This is the same as SPP mode except that
direction may be used to tri-state the data lines. Furthermore, reading the
data register returns the value on the data lines, not the value in the data
register.
Parallel Port FIFO mode. This is the same as SPP mode except that bytes
are written or DMAed to the FIFO. FIFO data are automatically transmitted
using the standard parallel port protocol. This mode is useful only when
direction is 0.
ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes
placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a
single FIFO and automatically transmitted to the peripheral using the ECP
Protocol. When the direction is 1 (reverse direction), bytes are moved from
the ECP parallel port and packed into bytes in the ecpDFifo.
EPP Mode. EPP mode is activated if the EPP mode is selected.
Reserved.
Test Mode. The FIFO may be written and read in this mode, but the data is
not transmitted on the parallel port.
Configuration Mode. The confgA and confgB registers are accessible at
0x400 and 0x401 in this mode.
-128-
DESCRIPTION
W83627UHG